Yosys sat -prove segfaults on a design containing a memory read

opt_reduce: $pmux input dedup emits inputs in dict (hash) order instead of source order, causing QoR regression

Yosys crash when module output signal name same as module name

opt_clean after proc changes simulation result for explicitly-driven output bit

issues with new CMake based build

Check command fails with undriven nets

16 failing tests in tests/aiger when building Fedora RPM

Verilog backend struggles with multidimensional array indices into array dimensions from Verific frontend that are non-PoT and/or don't start from zero

always_latch incorrectly tries to latch address of an array

First open-source NPU tape-out with Yosys/OpenROAD flow