Yosys 0.62 .. Yosys 0.63 -------------------------- * Various - Added DSP inference for Gowin GW1N and GW2A. - Added support for subtract in preadder for Xilinx arch. - Added infrastructure to run a sat solver as a command. * New commands and options - Added "-ignore-unknown-cells" option to "equiv_induct" and "equiv_simple" pass. - Added "-force-params" option to "memory_libmap" pass. - Added "-select-solver" option to "sat" pass. - Added "-default_params" option to "write_verilog" pass. - Added "-nodsp" option to "synth_gowin" pass.

Yosys 0.61 .. Yosys 0.62 -------------------------- * Various - verific: Added "-sv2017" flag option to support System Verilog 2017. - verific: Added VHDL related flags to "-f" and "-F" and support reading VHDL file from file lists. - Updated cell libs with proper module declaration where non standard (...) style was used. * New commands and options - Added "-word" option to "lut2mux" pass to enable emitting word level cells. - Added experimental "opt_balance_tree" pass to convert cascaded cells into tree of cells to improve timing. - Added "-gatesi" option to "write_blif" pass to init gates under gates_mode in BLIF format. - Added "-on" and "-off" options to "debug" pass for persistent debug logging. - Added "linux_perf" pass to control performance recording.

Yosys 0.59 .. Yosys 0.60 -------------------------- * Various - read_verilog: suport unsized parameters. - Added static library compile option. * New commands and options - Added "sdc" pass for reading SDC files. - Added experimental "sdc_expand" and "opensta" for OpenSTA integration. - Added "icell_liberty" pass for used internal cells.

Yosys 0.57 .. Yosys 0.58 -------------------------- * Various - Run ABC passes in parallel. - Extending support for buffer normalization. - Overhaul of logging APIs. - read_blif: Represent sequential elements with gate cells. - Support multiple lib files in abc9_exe. * New commands and options - Added "-wireshape" option to "show" command to allow control the shape of wire nodes. - Added "-relativeshare" option to "read_verilog", "synth" and "techmap" pass for synthesis reproducibility testing. - "write_rtlil" pass no longer sorts design, added "-sort" option to match old behavior - Added "-sva-continue-on-err" to "verific" pass to allow processing designs that includes unsupported SVA.

Yosys 0.53 .. Yosys 0.54 -------------------------- * New commands and options - Added "-genlib" option to "abc_new" and "abc9_exe" passes. - Added "-verbose" and "-quiet" options to "libcache" pass. - Added "-no-sort" option to "write_aiger" pass. * Various - Added "muldiv_c" peepopt. - Accept (and ignore) SystemVerilog unique/priority if. - "read_verilog" copy inout ports in and out of functions/tasks. - Enable single-bit vector wires in RTLIL. * Xilinx support - Single-port URAM mapping to support memories 2048 x 144b

Yosys 0.52 .. Yosys 0.53 -------------------------- * New commands and options - Added "constmap" pass for technology mapping of coarse constant value. - Added "timeest" pass to estimate the critical path in clock domain. - Added "-blackbox" option to "cutpoint" pass to cut all instances of blackboxes. - Added "-noscopeinfo" option to "cutpoint" pass. - Added "-nocleanup" option to "flatten" pass to prevent removal of unused submodules. - Added "-declockgate" option to "formalff" pass that turns clock gating into clock enables. * Various - Added "$scopeinfo" cells to preserve information during "cutpoint" pass. - Added dataflow tracking documentation. - share: Restrict activation patterns to potentially relevant signal. - liberty: More robust parsing. - verific: bit blast RAM if using mem2reg attribute.

Yosys 0.51 .. Yosys 0.52 -------------------------- * New commands and options - Added "-pattern-limit" option to "share" pass to limit analysis effort. - Added "libcache" pass to control caching of technology library data parsed from liberty files. - Added "read_verilog_file_list" to parse verilog file list. * Various - Added $macc_v2 cell. - Improve lexer performance and zlib support for "read_liberty". - opt_expr: optimize pow of 2 cells.

Yosys 0.49 .. Yosys 0.50 -------------------------- * Various - "write_verilog" emits "$check" cell names as labels.