Yosys crash when module output signal name same as module name
pending-verification
### Version
Yosys 0.66+70 (git sha1 8eb313307, Release, Clang /usr/bin/clang++ 18.1.8)
### On which OS did this happen?
Linux
### Reproduction Steps
With source:
```
module pdm #(
parameter PHY = "zero"
)(
output wire pdm,
);
if (PHY == "zero") begin
assign pdm = 1'b0;
end
endmodule
```
and command line of:
```
yosys -p 'synth_ice40 -top pdm ' pdm.v
```
### Expected Behavior
Yosys should run to completion without crashing.
### Actual Behavior
Yosys runs and then crashes with the following output:
```
2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm'.
Generating RTLIL representation for module `\pdm'.
terminate called after throwing an instance of 'std::out_of_range'
what(): basic_string::at: __n (which is 4) >= this->size() (which is 4)
Aborted (core dumped)
```
This has been observed on several versions of yosys going back some time, however it is *not* seen on much older versions. Yosys 0.42+15 (git sha1 2fd2b6538, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) works fine for example.
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