always_latch incorrectly tries to latch address of an array

### Version Yosys 0.64 (git sha1 d8dab5b32666564eca8e18f412973853ce006e61, g++ 15.2.1_p20260214 -fPIC -O3) ### On which OS did this happen? Linux ### Reproduction Steps Hello, I'm having an issue with using always latch on SystemVerilog similar to the following ``` always_latch register[addr] = data; ``` It tries to treat addr as a latch as well, the only workaround is using a case statement with every variation of addr and statically addressing via the case. The error is the following, after running `proc` ``` ERROR: No latch inferred for signal `\registers.$mem2reg_rd$\regs$registers.sv:25$1_ADDR' from always_latch process `\registers.$proc$registers.sv:4$5'. ``` ### Expected Behavior Correct processing of Verilog always_latch. ### Actual Behavior `ERROR: No latch inferred for signal `\registers.$mem2reg_rd$\regs$registers.sv:25$1_ADDR' from always_latch process `\registers.$proc$registers.sv:4$5'`