Check command fails with undriven nets

### Version Yosys 0.64 (git sha1 d8dab5b32666564eca8e18f412973853ce006e61, clang++ 21.1.2 -fPIC -O3) ### On which OS did this happen? Linux ### Reproduction Steps Run yosys, read and check the verilog: ``` yosys> read_verilog src/uart_tx.v yosys> check ``` This module has been taped out a few times successfully. This problem is also present in `Yosys 0.63+184 (git sha1 240439bdb, clang++ 18.1.8 -fPIC -O3)` but not `Yosys 0.62+112 (git sha1 687a36af3, clang++ 18.1.8 -fPIC -O3)` uart_tx.v can be found at https://github.com/MichaelBell/wafer-space-repro/blob/yosys-issue/src/uart_tx.v (apparently I can't attach verilog files?) ### Expected Behavior ``` yosys> read_verilog ../../yosys-repro/src/uart_tx.v 1. Executing Verilog-2005 frontend: ../../yosys-repro/src/uart_tx.v Parsing Verilog input from `../../yosys-repro/src/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. yosys> check 2. Executing CHECK pass (checking for obvious problems). Checking module uart_tx... Found and reported 0 problems. yosys> ``` ### Actual Behavior ``` yosys> read_verilog src/uart_tx.v 1. Executing Verilog-2005 frontend: src/uart_tx.v Parsing Verilog input from `src/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. yosys> check 2. Executing CHECK pass (checking for obvious problems). Checking module uart_tx... Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.tx_en is used but has no driver. Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [3] is used but has no driver. Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [2] is used but has no driver. Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [1] is used but has no driver. Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [0] is used but has no driver. Found and reported 5 problems. ```