## [AMD] * Adding Ryzen Z2 A and Ryzen AI Z2 Extreme * [Turin][Dense] Complete the EPYC Embedded 9005 Series * Adding the Ryzen 5 5500X3D processor * Complete the Ryzen 8000 Series * [Zen5][SHP] Introducing the Shimada Peak architecture * [Family 15h] Provides Package voltage from Core aggregation ## [Intel] * [Skylake/X] Provides Package voltage from Core aggregation ## [x86_64] * [Virtualization] Initialized `DCU_Mask` bitmask ## [aarch64] * Pass explicit variable-immediate type to fix assembly ## [Doc] * README for Fedora Copr repository * ## [Build] * [x86_64] Fedora v34 api fix detecting `RHEL MINOR` `99` * [Kernel][aarch64] Set `mcelsius` based on `thermal_zone_get_temp()` * [Kernel] Preparing for the impacts of kernel version `6.18`

## [Code Review] * Restrict module parameters to load-time only ## [AMD] ### [Genoa] * Attempt SOC voltage reading * Apply monitoring interval to RAM consumption calculation ### [Kernel] * Use `CONFIG_AMD_NB` to call SMU if kernel version ≥ 6.0 ## [Intel] ### [Core Ultra] * Updated register names and addresses ### [Alder Lake/N] * Added "Twin Lake" and "Amston Lake" codenames ## [x86_64] * Added `lock` prefix to bit operations for cross-package atomicity ## [AArch64] [RISC-V] [PowerPC] * Improved CPU topology detection to identify the BSP (Boot Strap Processor)

## [UI] * Increased length of L3 cache digits in header * [MC] Renamed `Disabled` to `Undefined` channels * [CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number * Display `N/A` when Intel processor is not HDC capable ## [Code Review] * Refactored variable names for inclusivity * [Kernel] VT-d: request memory region before use * uBench: Code clean-up ## [Doc] * README for Rocky Linux and Clear Linux ## [Build] * Prevent module loading if detected CPU count > CORE_COUNT (case of EPYC with 384 CPUs) * Make static the PCI list to comply with kernel frame size * Kernel 6.15 is switching to use `hrtimer_setup()` * [CI] Bump to uraimo version 3 * `of_root` defined since Kernel `3.19` * Replaced inline C functions with static or macro * Kernel 6.14 `node_to_amd_nb()` workaround * Added `CONFIG_ACPI_CPPC_LIB` to conditionally build EPP * Changed some `inline` function prototypes ## [AMD] ### [Zen] * Count DIMM ranks from the enabled chip select * Now conducts Datafabric calls through Kernel PCI * [HSMP] Provides its own lock rather than SMN' lock * [HSMP] arguments index fix in `CONFIG_AMD_NB` build mode * [HSMP] Check mailbox protocol is correctly functioning using the arithmetic addition `2 + 1 = 3` * Replaced package thermal with a pointer function * Specifications of some Zen registers * Adding "Strix Halo" and "Krackan Point" architectures * Adding "Fire Range" series * Adding Ryzen Z2 series ### [Genoa] * Probe up to four memory controllers * Improved EPYC Genoa support: * CCD and CCX topology fixed to compute the right thermal SMU address * Increase `BIT_IO_RETRIES_COUNT` to parallelize `HSMP_RD_DIMM_PWR` calls * Added specifics for an "Eng Sample" of Genoa architecture * Accumulate the power consumed by RAM * Attempt to monitor DIMM power consumption from HSMP * Use generic voltage & power ### [Hawk Point] * Set `AddrCfg` & `DimmCfg` addresses for Phoenix UMC ### [Family 1Ah] * Added the HSMP for EPYC Turin ## [Intel] ### [MTL][ARL] * Improving MC Bus and DDR speed to follow OC SOC * Refactored IMC decoder to query DDR clock * Merged the P-core and E-core monitoring loops * Get/Set `L1_NPP_Prefetch` from `MSR_MISC_FEATURE_CONTROL` * Provide monitoring functions to Arrow Lake * Also applying to Lunar Lake * Grant `ODCM` and `PWR MGMT` accesses to MTL, ARL, Lunar Lake * New features for `Core Ultra 7 265K` ## [x86_64] * Order SMBIOS DIMM list by channel * [IMC] Can display Twelve Channel memory controller * SMBIOS dump resized to 12 channels multiplied 4 DIMM slots * Compute the SMBIOS DIMM part number (rev 2) * Check HCF capability for MPERF/APERF MSR access in VM ## [AArch64] [RISC-V] [PowerPC] * [riscv64] Fill with the Machine Architecture ID Register `marchid` * [ppc64] Added source comment * [riscv64][ppc64] Improving Hybrid processor detection * [ppc64] Fix the Carry flag asm code * [ppc64] The processor version register (PVR) is a 32-bit register * [ppc64] Use MFXER to get the XER * Raise the Carry Flag * [ppc64][riscv64] ASM instructions for uBench macros * [aarch64] Checking `CSSELR` and `CCSIDR` registers in ARMv9 * [aarch64] If FEAT_CCIDX implemented read NumSets from upper reg * [aarch64] Safely access the PMU registers * Detect the Android AVF hypervisor * Comment PMC in uBench macros * [ppc64] Detect the IBM POWER10 Functional Simulator * [aarch64][riscv64][ppc64] Improving DT integration to detect VM * [AArch64] Improving virtualization detection from Device Tree * [ppc64][riscv64] Device Tree fetching based on kernel version * [PowerPC] Preliminary port to the `ppc64le` architecture * [riscv64] Adding vendor Microchip * [riscv64] Attempt to read the Hart ID from device tree * [riscv64] Restore PMU counter delta calculation * [riscv64] `mvendorid` & `marchid` based architecture qualification * [riscv64] Specification of `SSTATUS` and `SCOUNTEREN` registers * [riscv64] Normalize counters to work with unaccurate QEMU cycles * [riscv64] Attempt to enable the Cycle and Instruction counters * [riscv64] Read the performance cycles using `rdcycle` * [riscv64] Read the retired instructions counter using `rdinstret` * [riscv64] Get the TSC from `rdtime` instruction * [riscv64] Comment out any reading of cycles * [RISC-V] Code clean-up to debug start-up * [RISC-V] Preliminary port of the riscv64 architecture ---- ## CoreFreq ISO SHA1 of the attached image ```console 2d06766b6aea94e7b7a9fff4415e351d6dca9657 ```

# [Build] * Implement `amd_pci_dev_to_node_id` from Kernel `6.14` * [CI] Pin build environment to ubuntu-22.04 (thanks @jlacvdr) * Allow changing WARNING variable from command line (thanks @s-stepien) # [AMD] * [Strix Point] Attempt to decode UMC and IOMMU controllers * [Raphael] Adding Ryzen 5 7400F * [Granite Ridge] Adding Ryzen 5 9600

Production version

# [Build] * [x86_64] AlmaLinux 9.5 (Teal Serval) compilation fix * [UI] Fix System Registers window for a 3 digits CPU id number # [Doc] * SSH how to run the UI # [AArch64] * Checking specification of Memory Model Feature Registers * Aggregate and display ISA features of `ID_AA64ISAR3_EL1` * Instruction Set Attribute Register 3 `ID_AA64ISAR3_EL1` * Processor Feature Register 2 `AA64PFR2_EL1` * Display FP and SIMD bits from `MVFR` * Added remaining `CLRBHB` and `PCDPHINT` of `ISAR2` * Display the Streaming Vector Control Register `SVCR` * Query and export the Media and VFP Feature Registers `MVFR` * Display, export Floating-point Control Register `FPCR` * Architectural Feature Access Control Register `CPACR` * Display the Hypervisor Configuration Register `HCR_EL2` based on `CurrentEL` # [AMD] * [VERMEER] Adding Ryzen 5 5600XT and 5600T processors * [Zen 5c] Fixed EPYC Turin-Dense series ---- # CoreFreq ISO Instructions in Wiki / [LiveCD](https://github.com/cyring/CoreFreq/wiki/Live-CD) SHA1 of the attached image ``` b696f1d7de5871d72bf1c177b7cce5ef490b4711 ```

# [AMD] * [Family 1Ah][Granite Ridge] * P-State programming fix * Merge PCI identifier lists * Reserve the `BTC-NOBR` aggregation to Zen2 architecture # [AArch64] * Query and JSON export Hypervisor Configuration Register `HCR_EL2` * Experimental mode required ---- # _CoreFreq_ ISO Instructions in Wiki / [LiveCD](https://github.com/cyring/CoreFreq/wiki/Live-CD) SHA1 of the attached image ``` dd583e8855f98d9c62dba1b25a099c5f22dd2738 ```

# [AMD] * [V2000 Series] Adding the Ryzen Embedded V2A46 * [Family 1Ah][All Families] Refactoring topology for CCD cluster Confirmed `7950X`, `3950X` # [Intel] * ODCM is confirmed working on Raptor Lake architecture Confirmed `i9-14900K` # [UI] * Increased max ratio in HWP condition to avoid a zero frequency Confirmed `i9-14900K` # [Build] * Print other variables from Makefile recipe info `CORE_COUNT` `TASK_ORDER` `MAX_FREQ_HZ` `HWM_CHIPSET` ## [CI] * [AArch64] Commenting out the `debian-testing` and `alpine-latest` # [Doc] * Mention the AMD family 1Ah support in README ---- # CoreFreq ISO Instructions in Wiki / [LiveCD](https://github.com/cyring/CoreFreq/wiki/Live-CD) SHA1 of the attached image ``` 41492ffb91a987b34b71f021d7a4d19aca24a276 ```