Support for TOML or JSON files
Hi!
I recently found this awesome contribution for the typst project.
I was wondering that, the current process of defining a circuit is quite verbose and boiler-plate and if this could be automated/supported using the configuration/description of the circuit given in either `.toml` or `.json` files (both of which have native typst support).
For example,
[typst-timetable](https://github.com/ludwig-austermann/typst-timetable/blob/main/example/2023.toml) accepts a `.toml` file to generate a table, which is a quite convenient approach.
An example of how a digital circuit can be expressed in json files,
`XOR.json`
```
[
{
"inputs": [
{
"inputs": [
{
"inputs": [],
"name": "A"
},
{
"inputs": [
{
"inputs": [],
"name": "B"
}
],
"name": "NOT"
}
],
"name": "AND"
},
{
"inputs": [
{
"inputs": [],
"name": "B"
},
{
"inputs": [
{
"inputs": [],
"name": "A"
}
],
"name": "NOT"
}
],
"name": "AND"
}
],
"name": "OR"
}
]
```
But again, this is too much boilerplate, than something similar expressed in a `.toml` file.
Also, `.toml` can be a better choice for this kind of requirement, as analogue as well as digital circuits can easily become complex (interconnections between different parts of the circuit, intricate wiring), which a `.json` template like above cannot handle (no wiring details). Tho, we can a template like, an array for listing all the components and an array to mention all the wiring between inputs and outputs of different components.
I would like to know if there's any plan for such support?
As, I worked on a project called [logic-sim](https://github.com/saadulkh/logic-sim), I want to continue this project in future as well. And this project can generate output descriptions of the digital circuits, as shown above. Was wondering to integrate both these projects to make things easier.
关闭于 2023-05-28 2 条评论