Issue with SDRAM on QMTech clone boards with ESMT M12L5121632A-5T

The core works correctly on: DE10-Nano with memory board QMTech board with Alliance AS4C32M16SB-7TIN SDRAM Noname QMTech clones using the same Alliance SDRAM However, it does not work on a clone board with ESMT M12L5121632A-5T (faster) SDRAM. Memory tests on this board pass flawlessly at the maximum supported SDRAM frequency (167 MHz). The only differences between the chips are initialization sequence requirements and absolute maximum ratings: Initialization Alliance: Requires CKE = LOW at power-up, wait ≥200 µs with stable clock, then set CKE HIGH before issuing PRECHARGE/REFRESH/MRS. [Alliance datasheet](https://www.alliancememory.com/wp-content/uploads/AllianceMemory_512M_SDRAM_Bdie_AS4C32M16SB-7TXN-6TIN-7BIN__Rev1.4_June2024NK.pdf?utm_source=chatgpt.com) ESMT: Requires CKE = HIGH during power-up, wait ≥200 µs while keeping NOP, then issue PRECHARGE/REFRESH/MRS (CKE must be HIGH before MRS). [ESMT datasheet](https://datasheet4u.com/pdf-down/M/1/2/M12L5121632A-ESMT.pdf?utm_source=chatgpt.com) Absolute Maximum Ratings / Overshoot Alliance: Allows I/O overshoot up to 4.6 V (≤3 ns pulses). ESMT: Absolute max is 4.0 V on any pin. VIH(max) = VDD + 0.3 V, with short-pulse exception only up to 4.0 V. → In practice, ESMT seems more sensitive to power/IO overshoot. Additional Notes The ao486 core running with profile “Max (unstable)” (Dec 2024 build) works fine on DE10-Nano, but fails on QMTech and its clones (with Alliance and ESMT) . The “unstable” (Aug 2025) build works on all clones. This may suggest that slower chips + longer traces on DE10-Nano + imperfect routing of its memory module (unequal signal lengths, parasitic capacitance/inductance) actually suppress interference. As the owner of both: DE10-Nano + Alliance 128 MB SDRAM QMTech-clone board with ESMT “fast” SDRAM …I’d like to volunteer for testing experimental builds. I think i'm able to build this core (I saw in a0486 repo advices how to build core under linux environment and hope it is applicable to this repo as well). It would be great if someone could assist or suggest which parameters in the source code should be adjusted so I can build (in corner case I'll run VM with Windows) and test on both boards. If there’s no interest from others, I’ll simply return the noname board to the seller. P.S. I duplicated this issue in https://github.com/MiSTer-devel/N64_MiSTer/issues/83 Sorry if it (duplication) violate rules.