%{
#include <string.h>
%}
%pic
%compare-strncmp
%language=ANSI-C
%readonly-tables
%define lookup-function-name is_keyword_c_builtin
%%
COSMOPOLITAN_CXX_END_
COSMOPOLITAN_CXX_START_
COSMOPOLITAN_CXX_USING_
COSMOPOLITAN_C_END_
COSMOPOLITAN_C_START_
STRINGIFY
__ATOMIC_ACQUIRE
__ATOMIC_ACQ_REL
__ATOMIC_CONSUME
__ATOMIC_RELAXED
__ATOMIC_RELEASE
__ATOMIC_SEQ_CST
__atomic_add_fetch
__atomic_always_lock_free
__atomic_and_fetch
__atomic_clear
__atomic_compare_exchange
__atomic_compare_exchange_n
__atomic_exchange
__atomic_exchange_n
__atomic_fetch_add
__atomic_fetch_and
__atomic_fetch_nand
__atomic_fetch_or
__atomic_fetch_sub
__atomic_fetch_xor
__atomic_is_lock_free
__atomic_load
__atomic_load_n
__atomic_nand_fetch
__atomic_or_fetch
__atomic_signal_fence
__atomic_store
__atomic_store_n
__atomic_sub_fetch
__atomic_test_and_set
__atomic_thread_fence
__atomic_xor_fetch
__builtin_FILE
__builtin_FUNCTION
__builtin_LINE
__builtin___clear_cache
__builtin___fprintf_chk
__builtin___memcpy_chk
__builtin___memmove_chk
__builtin___mempcpy_chk
__builtin___memset_chk
__builtin___printf_chk
__builtin___snprintf_chk
__builtin___sprintf_chk
__builtin___stpcpy_chk
__builtin___strcat_chk
__builtin___strcpy_chk
__builtin___strncat_chk
__builtin___strncpy_chk
__builtin___strub_enter
__builtin___strub_leave
__builtin___strub_update
__builtin___vfprintf_chk
__builtin___vprintf_chk
__builtin___vsnprintf_chk
__builtin___vsprintf_chk
__builtin_aarch64_get_fpcr
__builtin_aarch64_get_fpcr64
__builtin_aarch64_get_fpsr
__builtin_aarch64_get_fpsr64
__builtin_aarch64_set_fpcr
__builtin_aarch64_set_fpcr64
__builtin_aarch64_set_fpsr
__builtin_aarch64_set_fpsr64
__builtin_abs
__builtin_add_overflow
__builtin_add_overflow_p
__builtin_addc
__builtin_addcl
__builtin_addcll
__builtin_addf128_round_to_odd
__builtin_addg6s
__builtin_alloc
__builtin_alloc_with_align
__builtin_alloca
__builtin_alloca_with_align
__builtin_alloca_with_align_and_max
__builtin_alpha_amask
__builtin_alpha_cmpbge
__builtin_alpha_ctlz
__builtin_alpha_ctpop
__builtin_alpha_cttz
__builtin_alpha_extbl
__builtin_alpha_extlh
__builtin_alpha_extll
__builtin_alpha_extqh
__builtin_alpha_extql
__builtin_alpha_extwh
__builtin_alpha_extwl
__builtin_alpha_implver
__builtin_alpha_insbl
__builtin_alpha_inslh
__builtin_alpha_insll
__builtin_alpha_insqh
__builtin_alpha_insql
__builtin_alpha_inswh
__builtin_alpha_inswl
__builtin_alpha_maxsb8
__builtin_alpha_maxsw4
__builtin_alpha_maxub8
__builtin_alpha_maxuw4
__builtin_alpha_minsb8
__builtin_alpha_minsw4
__builtin_alpha_minub8
__builtin_alpha_minuw4
__builtin_alpha_mskbl
__builtin_alpha_msklh
__builtin_alpha_mskll
__builtin_alpha_mskqh
__builtin_alpha_mskql
__builtin_alpha_mskwh
__builtin_alpha_mskwl
__builtin_alpha_perr
__builtin_alpha_pklb
__builtin_alpha_pkwb
__builtin_alpha_rpcc
__builtin_alpha_umulh
__builtin_alpha_unpkbl
__builtin_alpha_unpkbw
__builtin_alpha_zap
__builtin_alpha_zapnot
__builtin_apply
__builtin_apply_args
__builtin_arc_align
__builtin_arc_aligned
__builtin_arc_brk
__builtin_arc_clri
__builtin_arc_core_read
__builtin_arc_core_write
__builtin_arc_divaw
__builtin_arc_dmach
__builtin_arc_dmachu
__builtin_arc_dmacwh
__builtin_arc_dmacwhu
__builtin_arc_dmpyh
__builtin_arc_dmpyhu
__builtin_arc_ffs
__builtin_arc_flag
__builtin_arc_fls
__builtin_arc_kflag
__builtin_arc_lr
__builtin_arc_mul64
__builtin_arc_mulu64
__builtin_arc_nop
__builtin_arc_norm
__builtin_arc_normw
__builtin_arc_qmach
__builtin_arc_qmachu
__builtin_arc_qmpyh
__builtin_arc_qmpyhu
__builtin_arc_rtie
__builtin_arc_seti
__builtin_arc_sleep
__builtin_arc_someinsn
__builtin_arc_sr
__builtin_arc_swap
__builtin_arc_swi
__builtin_arc_sync
__builtin_arc_trap_s
__builtin_arc_unimp_s
__builtin_arc_vabsaw
__builtin_arc_vabsw
__builtin_arc_vaddaw
__builtin_arc_vaddsub
__builtin_arc_vaddsub2h
__builtin_arc_vaddsub4h
__builtin_arc_vaddsuw
__builtin_arc_vaddw
__builtin_arc_vand
__builtin_arc_vandaw
__builtin_arc_vasrpwbi
__builtin_arc_vasrrpwbi
__builtin_arc_vasrrwi
__builtin_arc_vasrsrwi
__builtin_arc_vasrw
__builtin_arc_vasrwi
__builtin_arc_vavb
__builtin_arc_vavrb
__builtin_arc_vbaddw
__builtin_arc_vbic
__builtin_arc_vbicaw
__builtin_arc_vbmaxw
__builtin_arc_vbminw
__builtin_arc_vbmulaw
__builtin_arc_vbmulfw
__builtin_arc_vbmulw
__builtin_arc_vbrsubw
__builtin_arc_vbsubw
__builtin_arc_vd6tapf
__builtin_arc_vdifaw
__builtin_arc_vdifw
__builtin_arc_vdirun
__builtin_arc_vdiwr
__builtin_arc_vdorun
__builtin_arc_vdowr
__builtin_arc_vendrec
__builtin_arc_veqw
__builtin_arc_vexch1
__builtin_arc_vexch2
__builtin_arc_vexch4
__builtin_arc_vh264f
__builtin_arc_vh264ft
__builtin_arc_vh264fw
__builtin_arc_vld128
__builtin_arc_vld32
__builtin_arc_vld32wh
__builtin_arc_vld32wl
__builtin_arc_vld64
__builtin_arc_vld64w
__builtin_arc_vlew
__builtin_arc_vltw
__builtin_arc_vmac2h
__builtin_arc_vmac2hu
__builtin_arc_vmaxaw
__builtin_arc_vmaxw
__builtin_arc_vminaw
__builtin_arc_vminw
__builtin_arc_vmovaw
__builtin_arc_vmovw
__builtin_arc_vmovzw
__builtin_arc_vmpy2h
__builtin_arc_vmpy2hu
__builtin_arc_vmr1aw
__builtin_arc_vmr1w
__builtin_arc_vmr2aw
__builtin_arc_vmr2w
__builtin_arc_vmr3aw
__builtin_arc_vmr3w
__builtin_arc_vmr4aw
__builtin_arc_vmr4w
__builtin_arc_vmr5aw
__builtin_arc_vmr5w
__builtin_arc_vmr6aw
__builtin_arc_vmr6w
__builtin_arc_vmr7aw
__builtin_arc_vmr7w
__builtin_arc_vmrb
__builtin_arc_vmulaw
__builtin_arc_vmulfaw
__builtin_arc_vmulfw
__builtin_arc_vmulw
__builtin_arc_vmvaw
__builtin_arc_vmvw
__builtin_arc_vmvzw
__builtin_arc_vnew
__builtin_arc_vor
__builtin_arc_vrec
__builtin_arc_vrecrun
__builtin_arc_vrun
__builtin_arc_vsignw
__builtin_arc_vsr8
__builtin_arc_vsr8aw
__builtin_arc_vsr8awi
__builtin_arc_vsr8i
__builtin_arc_vst128
__builtin_arc_vst16_n
__builtin_arc_vst32_n
__builtin_arc_vst64
__builtin_arc_vsubadd
__builtin_arc_vsubadd2h
__builtin_arc_vsubadd4h
__builtin_arc_vsubaw
__builtin_arc_vsubw
__builtin_arc_vsummw
__builtin_arc_vupbaw
__builtin_arc_vupbw
__builtin_arc_vupsbaw
__builtin_arc_vupsbw
__builtin_arc_vvc1f
__builtin_arc_vvc1ft
__builtin_arc_vxor
__builtin_arc_vxoraw
__builtin_assoc_barrier
__builtin_assume
__builtin_assume_aligned
__builtin_avr_cli
__builtin_avr_delay_cycles
__builtin_avr_flash_segment
__builtin_avr_fmul
__builtin_avr_fmuls
__builtin_avr_fmulsu
__builtin_avr_insert_bits
__builtin_avr_nop
__builtin_avr_nops
__builtin_avr_sei
__builtin_avr_sleep
__builtin_avr_swap
__builtin_avr_wdr
__builtin_bcdadd
__builtin_bcdadd_eq
__builtin_bcdadd_gt
__builtin_bcdadd_lt
__builtin_bcdadd_ov
__builtin_bcdsub
__builtin_bcdsub_eq
__builtin_bcdsub_ge
__builtin_bcdsub_gt
__builtin_bcdsub_le
__builtin_bcdsub_lt
__builtin_bcdsub_ov
__builtin_bit_cast
__builtin_bpermd
__builtin_bpf_load_byte
__builtin_bpf_load_half
__builtin_bpf_load_word
__builtin_bswap128
__builtin_bswap16
__builtin_bswap32
__builtin_bswap64
__builtin_btf_type_id
__builtin_byte_in_either_range
__builtin_byte_in_range
__builtin_byte_in_set
__builtin_call_with_static_chain
__builtin_calloc
__builtin_cbcdtd
__builtin_cdtbcd
__builtin_cfuged
__builtin_choose_expr
__builtin_classify_type
__builtin_clear_padding
__builtin_clrsb
__builtin_clrsbg
__builtin_clrsbl
__builtin_clrsbll
__builtin_clz
__builtin_clzg
__builtin_clzl
__builtin_clzll
__builtin_cmpb
__builtin_cntlzdm
__builtin_cnttzdm
__builtin_complex
__builtin_constant_p
__builtin_convertvector
__builtin_copysignfn
__builtin_copysignfnx
__builtin_copysignq
__builtin_cpu_init
__builtin_cpu_is
__builtin_cpu_supports
__builtin_crypto_vcipher
__builtin_crypto_vcipherlast
__builtin_crypto_vncipher
__builtin_crypto_vncipherlast
__builtin_crypto_vpermxor
__builtin_crypto_vpmsumb
__builtin_crypto_vpmsumd
__builtin_crypto_vpmsumh
__builtin_crypto_vpmsumw
__builtin_crypto_vsbox
__builtin_crypto_vshasigmad
__builtin_crypto_vshasigmaw
__builtin_ctz
__builtin_ctzg
__builtin_ctzl
__builtin_ctzll
__builtin_custom_fn
__builtin_custom_fnf
__builtin_custom_fnff
__builtin_custom_fnfi
__builtin_custom_fnfp
__builtin_custom_fni
__builtin_custom_fnif
__builtin_custom_fnii
__builtin_custom_fnip
__builtin_custom_fnp
__builtin_custom_fnpf
__builtin_custom_fnpi
__builtin_custom_fnpp
__builtin_custom_in
__builtin_custom_inf
__builtin_custom_inff
__builtin_custom_infi
__builtin_custom_infp
__builtin_custom_ini
__builtin_custom_inif
__builtin_custom_inii
__builtin_custom_inip
__builtin_custom_inp
__builtin_custom_inpf
__builtin_custom_inpi
__builtin_custom_inpp
__builtin_custom_n
__builtin_custom_nf
__builtin_custom_nff
__builtin_custom_nfi
__builtin_custom_nfp
__builtin_custom_ni
__builtin_custom_nif
__builtin_custom_nii
__builtin_custom_nip
__builtin_custom_np
__builtin_custom_npf
__builtin_custom_npi
__builtin_custom_npp
__builtin_custom_pn
__builtin_custom_pnf
__builtin_custom_pnff
__builtin_custom_pnfi
__builtin_custom_pnfp
__builtin_custom_pni
__builtin_custom_pnif
__builtin_custom_pnii
__builtin_custom_pnip
__builtin_custom_pnp
__builtin_custom_pnpf
__builtin_custom_pnpi
__builtin_custom_pnpp
__builtin_darn
__builtin_darn_32
__builtin_darn_raw
__builtin_ddedpd
__builtin_ddedpdq
__builtin_denbcd
__builtin_denbcdq
__builtin_dfp_dtstsfi_eq
__builtin_dfp_dtstsfi_eq_dd
__builtin_dfp_dtstsfi_eq_td
__builtin_dfp_dtstsfi_gt
__builtin_dfp_dtstsfi_gt_dd
__builtin_dfp_dtstsfi_gt_td
__builtin_dfp_dtstsfi_lt
__builtin_dfp_dtstsfi_lt_dd
__builtin_dfp_dtstsfi_lt_td
__builtin_dfp_dtstsfi_ov
__builtin_dfp_dtstsfi_ov_dd
__builtin_dfp_dtstsfi_ov_td
__builtin_dfp_quantize
__builtin_diex
__builtin_divde
__builtin_divdeu
__builtin_divf128_round_to_odd
__builtin_divwe
__builtin_divweu
__builtin_dscli
__builtin_dscliq
__builtin_dscri
__builtin_dscriq
__builtin_dxex
__builtin_dxexq
__builtin_dynamic_object_size
__builtin_eni
__builtin_expect
__builtin_expect_with_probability
__builtin_extend_pointer
__builtin_extract_return_addr
__builtin_fabsfn
__builtin_fabsfnx
__builtin_fabsq
__builtin_ffs
__builtin_ffsg
__builtin_ffsl
__builtin_ffsll
__builtin_flushd
__builtin_flushda
__builtin_fma
__builtin_fmaf128
__builtin_fmaf128_round_to_odd
__builtin_fpclassify
__builtin_fprintf
__builtin_fprintf_unlocked
__builtin_fputc
__builtin_fputc_unlocked
__builtin_fputs
__builtin_fputs_unlocked
__builtin_frame_address
__builtin_free
__builtin_frob_return_addr
__builtin_fwrite
__builtin_fwrite_unlocked
__builtin_get_texasr
__builtin_get_texasru
__builtin_get_tfhar
__builtin_get_tfiar
__builtin_goacc_parlevel_id
__builtin_goacc_parlevel_size
__builtin_has_attribute
__builtin_huge_val
__builtin_huge_valf
__builtin_huge_valfn
__builtin_huge_valfnx
__builtin_huge_vall
__builtin_huge_valq
__builtin_i32_clzero
__builtin_ia32_addpd
__builtin_ia32_addpd256
__builtin_ia32_addps
__builtin_ia32_addps256
__builtin_ia32_addsd
__builtin_ia32_addss
__builtin_ia32_addsubpd
__builtin_ia32_addsubpd256
__builtin_ia32_addsubps
__builtin_ia32_addsubps256
__builtin_ia32_aesdec128
__builtin_ia32_aesdeclast128
__builtin_ia32_aesenc128
__builtin_ia32_aesenclast128
__builtin_ia32_aesimc128
__builtin_ia32_aeskeygenassist128
__builtin_ia32_andnotsi256
__builtin_ia32_andnpd
__builtin_ia32_andnpd256
__builtin_ia32_andnps
__builtin_ia32_andnps256
__builtin_ia32_andpd
__builtin_ia32_andpd256
__builtin_ia32_andps
__builtin_ia32_andps256
__builtin_ia32_andsi256
__builtin_ia32_bextr_u32
__builtin_ia32_bextr_u64
__builtin_ia32_bextri_u32
__builtin_ia32_bextri_u64
__builtin_ia32_blendpd
__builtin_ia32_blendpd256
__builtin_ia32_blendps
__builtin_ia32_blendps256
__builtin_ia32_blendvpd
__builtin_ia32_blendvpd256
__builtin_ia32_blendvps
__builtin_ia32_blendvps256
__builtin_ia32_clflush
__builtin_ia32_clrssbsy
__builtin_ia32_cmpeqpd
__builtin_ia32_cmpeqps
__builtin_ia32_cmpeqsd
__builtin_ia32_cmpeqss
__builtin_ia32_cmpgepd
__builtin_ia32_cmpgeps
__builtin_ia32_cmpgtpd
__builtin_ia32_cmpgtps
__builtin_ia32_cmplepd
__builtin_ia32_cmpleps
__builtin_ia32_cmplesd
__builtin_ia32_cmpless
__builtin_ia32_cmpltpd
__builtin_ia32_cmpltps
__builtin_ia32_cmpltsd
__builtin_ia32_cmpltss
__builtin_ia32_cmpneqpd
__builtin_ia32_cmpneqps
__builtin_ia32_cmpneqsd
__builtin_ia32_cmpneqss
__builtin_ia32_cmpngepd
__builtin_ia32_cmpngeps
__builtin_ia32_cmpngtpd
__builtin_ia32_cmpngtps
__builtin_ia32_cmpnlepd
__builtin_ia32_cmpnleps
__builtin_ia32_cmpnlesd
__builtin_ia32_cmpnless
__builtin_ia32_cmpnltpd
__builtin_ia32_cmpnltps
__builtin_ia32_cmpnltsd
__builtin_ia32_cmpnltss
__builtin_ia32_cmpordpd
__builtin_ia32_cmpordps
__builtin_ia32_cmpordsd
__builtin_ia32_cmpordss
__builtin_ia32_cmppd
__builtin_ia32_cmppd256
__builtin_ia32_cmpps
__builtin_ia32_cmpps256
__builtin_ia32_cmpsd
__builtin_ia32_cmpss
__builtin_ia32_cmpunordpd
__builtin_ia32_cmpunordps
__builtin_ia32_cmpunordsd
__builtin_ia32_cmpunordss
__builtin_ia32_comieq
__builtin_ia32_comige
__builtin_ia32_comigt
__builtin_ia32_comile
__builtin_ia32_comilt
__builtin_ia32_comineq
__builtin_ia32_comisdeq
__builtin_ia32_comisdge
__builtin_ia32_comisdgt
__builtin_ia32_comisdle
__builtin_ia32_comisdlt
__builtin_ia32_comisdneq
__builtin_ia32_crc32di
__builtin_ia32_crc32hi
__builtin_ia32_crc32qi
__builtin_ia32_crc32si
__builtin_ia32_cvtdq2pd
__builtin_ia32_cvtdq2pd256
__builtin_ia32_cvtdq2ps
__builtin_ia32_cvtdq2ps256
__builtin_ia32_cvtpd2dq
__builtin_ia32_cvtpd2dq256
__builtin_ia32_cvtpd2pi
__builtin_ia32_cvtpd2ps
__builtin_ia32_cvtpd2ps256
__builtin_ia32_cvtpi2pd
__builtin_ia32_cvtpi2ps
__builtin_ia32_cvtps2dq
__builtin_ia32_cvtps2dq256
__builtin_ia32_cvtps2pd
__builtin_ia32_cvtps2pd256
__builtin_ia32_cvtps2pi
__builtin_ia32_cvtsd2si
__builtin_ia32_cvtsd2si64
__builtin_ia32_cvtsd2ss
__builtin_ia32_cvtsi2sd
__builtin_ia32_cvtsi2ss
__builtin_ia32_cvtsi642sd
__builtin_ia32_cvtss2sd
__builtin_ia32_cvtss2si
__builtin_ia32_cvttpd2dq
__builtin_ia32_cvttpd2dq256
__builtin_ia32_cvttpd2pi
__builtin_ia32_cvttps2dq
__builtin_ia32_cvttps2dq256
__builtin_ia32_cvttps2pi
__builtin_ia32_cvttsd2si
__builtin_ia32_cvttsd2si64
__builtin_ia32_cvttss2si
__builtin_ia32_divpd
__builtin_ia32_divpd256
__builtin_ia32_divps
__builtin_ia32_divps256
__builtin_ia32_divsd
__builtin_ia32_divss
__builtin_ia32_dppd
__builtin_ia32_dpps
__builtin_ia32_dpps256
__builtin_ia32_extract128i256
__builtin_ia32_extrq
__builtin_ia32_extrqi
__builtin_ia32_femms
__builtin_ia32_fxrstor
__builtin_ia32_fxrstor64
__builtin_ia32_fxsave
__builtin_ia32_fxsave64
__builtin_ia32_gatherdiv2df
__builtin_ia32_gatherdiv2di
__builtin_ia32_gatherdiv4df
__builtin_ia32_gatherdiv4di
__builtin_ia32_gatherdiv4sf
__builtin_ia32_gatherdiv4sf256
__builtin_ia32_gatherdiv4si
__builtin_ia32_gatherdiv4si256
__builtin_ia32_gathersiv2df
__builtin_ia32_gathersiv2di
__builtin_ia32_gathersiv4df
__builtin_ia32_gathersiv4di
__builtin_ia32_gathersiv4sf
__builtin_ia32_gathersiv4si
__builtin_ia32_gathersiv8sf
__builtin_ia32_gathersiv8si
__builtin_ia32_haddpd
__builtin_ia32_haddpd256
__builtin_ia32_haddps
__builtin_ia32_haddps256
__builtin_ia32_hsubpd
__builtin_ia32_hsubpd256
__builtin_ia32_hsubps
__builtin_ia32_hsubps256
__builtin_ia32_incsspd
__builtin_ia32_incsspq
__builtin_ia32_insert128i256
__builtin_ia32_insertps128
__builtin_ia32_insertq
__builtin_ia32_insertqi
__builtin_ia32_lddqu
__builtin_ia32_lddqu256
__builtin_ia32_lfence
__builtin_ia32_llwpcb16
__builtin_ia32_llwpcb32
__builtin_ia32_llwpcb64
__builtin_ia32_loaddqu
__builtin_ia32_loaddqu256
__builtin_ia32_loadhpd
__builtin_ia32_loadhps
__builtin_ia32_loadlpd
__builtin_ia32_loadlps
__builtin_ia32_loadss
__builtin_ia32_loadupd
__builtin_ia32_loadupd256
__builtin_ia32_loadups
__builtin_ia32_loadups256
__builtin_ia32_lwpins16
__builtin_ia32_lwpins32
__builtin_ia32_lwpins64
__builtin_ia32_lwpval16
__builtin_ia32_lwpval32
__builtin_ia32_lwpval64
__builtin_ia32_lzcnt_u16
__builtin_ia32_lzcnt_u32
__builtin_ia32_lzcnt_u64
__builtin_ia32_maskloadd
__builtin_ia32_maskloadd256
__builtin_ia32_maskloadpd
__builtin_ia32_maskloadpd256
__builtin_ia32_maskloadps
__builtin_ia32_maskloadps256
__builtin_ia32_maskloadq
__builtin_ia32_maskloadq256
__builtin_ia32_maskmovdqu
__builtin_ia32_maskmovq
__builtin_ia32_maskstored
__builtin_ia32_maskstored256
__builtin_ia32_maskstorepd
__builtin_ia32_maskstorepd256
__builtin_ia32_maskstoreps
__builtin_ia32_maskstoreps256
__builtin_ia32_maskstoreq
__builtin_ia32_maskstoreq256
__builtin_ia32_maxpd
__builtin_ia32_maxpd256
__builtin_ia32_maxps
__builtin_ia32_maxps256
__builtin_ia32_maxsd
__builtin_ia32_maxss
__builtin_ia32_mfence
__builtin_ia32_minpd
__builtin_ia32_minpd256
__builtin_ia32_minps
__builtin_ia32_minps256
__builtin_ia32_minsd
__builtin_ia32_minss
__builtin_ia32_monitor
__builtin_ia32_monitorx
__builtin_ia32_movddup256
__builtin_ia32_movhlps
__builtin_ia32_movlhps
__builtin_ia32_movmskpd
__builtin_ia32_movmskpd256
__builtin_ia32_movmskps
__builtin_ia32_movmskps256
__builtin_ia32_movntdq
__builtin_ia32_movntdqa
__builtin_ia32_movntdqa256
__builtin_ia32_movnti
__builtin_ia32_movnti64
__builtin_ia32_movntpd
__builtin_ia32_movntps
__builtin_ia32_movntq
__builtin_ia32_movntsd
__builtin_ia32_movntss
__builtin_ia32_movq128
__builtin_ia32_movsd
__builtin_ia32_movshdup
__builtin_ia32_movshdup256
__builtin_ia32_movsldup
__builtin_ia32_movsldup256
__builtin_ia32_movss
__builtin_ia32_mpsadbw128
__builtin_ia32_mpsadbw256
__builtin_ia32_mulpd
__builtin_ia32_mulpd256
__builtin_ia32_mulps
__builtin_ia32_mulps256
__builtin_ia32_mulsd
__builtin_ia32_mulss
__builtin_ia32_mwait
__builtin_ia32_mwaitx
__builtin_ia32_orpd
__builtin_ia32_orpd256
__builtin_ia32_orps
__builtin_ia32_orps256
__builtin_ia32_pabsb
__builtin_ia32_pabsb128
__builtin_ia32_pabsb256
__builtin_ia32_pabsd
__builtin_ia32_pabsd128
__builtin_ia32_pabsd256
__builtin_ia32_pabsw
__builtin_ia32_pabsw128
__builtin_ia32_pabsw256
__builtin_ia32_packssdw
__builtin_ia32_packssdw128
__builtin_ia32_packssdw256
__builtin_ia32_packsswb
__builtin_ia32_packsswb128
__builtin_ia32_packsswb256
__builtin_ia32_packusdw128
__builtin_ia32_packusdw256
__builtin_ia32_packuswb
__builtin_ia32_packuswb128
__builtin_ia32_packuswb256
__builtin_ia32_paddb
__builtin_ia32_paddb128
__builtin_ia32_paddb256
__builtin_ia32_paddd
__builtin_ia32_paddd128
__builtin_ia32_paddd256
__builtin_ia32_paddq
__builtin_ia32_paddq128
__builtin_ia32_paddq256
__builtin_ia32_paddsb
__builtin_ia32_paddsb256
__builtin_ia32_paddsw
__builtin_ia32_paddsw256
__builtin_ia32_paddusb
__builtin_ia32_paddusb256
__builtin_ia32_paddusw
__builtin_ia32_paddusw256
__builtin_ia32_paddw
__builtin_ia32_paddw128
__builtin_ia32_paddw256
__builtin_ia32_palignr
__builtin_ia32_palignr128
__builtin_ia32_palignr256
__builtin_ia32_pand
__builtin_ia32_pand128
__builtin_ia32_pandn
__builtin_ia32_pandn128
__builtin_ia32_pause
__builtin_ia32_pavgb
__builtin_ia32_pavgb128
__builtin_ia32_pavgb256
__builtin_ia32_pavgusb
__builtin_ia32_pavgw
__builtin_ia32_pavgw128
__builtin_ia32_pavgw256
__builtin_ia32_pblendd128
__builtin_ia32_pblendd256
__builtin_ia32_pblendvb128
__builtin_ia32_pblendvb256
__builtin_ia32_pblendw128
__builtin_ia32_pblendw256
__builtin_ia32_pbroadcastb128
__builtin_ia32_pbroadcastb256
__builtin_ia32_pbroadcastd128
__builtin_ia32_pbroadcastd256
__builtin_ia32_pbroadcastq128
__builtin_ia32_pbroadcastq256
__builtin_ia32_pbroadcastw128
__builtin_ia32_pbroadcastw256
__builtin_ia32_pclmulqdq128
__builtin_ia32_pcmpeqb
__builtin_ia32_pcmpeqb128
__builtin_ia32_pcmpeqb256
__builtin_ia32_pcmpeqd
__builtin_ia32_pcmpeqd128
__builtin_ia32_pcmpeqd256
__builtin_ia32_pcmpeqq
__builtin_ia32_pcmpeqq256
__builtin_ia32_pcmpeqw
__builtin_ia32_pcmpeqw128
__builtin_ia32_pcmpeqw256
__builtin_ia32_pcmpestri128
__builtin_ia32_pcmpestria128
__builtin_ia32_pcmpestric128
__builtin_ia32_pcmpestrio128
__builtin_ia32_pcmpestris128
__builtin_ia32_pcmpestriz128
__builtin_ia32_pcmpestrm128
__builtin_ia32_pcmpgtb
__builtin_ia32_pcmpgtb128
__builtin_ia32_pcmpgtb256
__builtin_ia32_pcmpgtd
__builtin_ia32_pcmpgtd128
__builtin_ia32_pcmpgtd256
__builtin_ia32_pcmpgtq
__builtin_ia32_pcmpgtq256
__builtin_ia32_pcmpgtw
__builtin_ia32_pcmpgtw128
__builtin_ia32_pcmpgtw256
__builtin_ia32_pcmpistri128
__builtin_ia32_pcmpistria128
__builtin_ia32_pcmpistric128
__builtin_ia32_pcmpistrio128
__builtin_ia32_pcmpistris128
__builtin_ia32_pcmpistriz128
__builtin_ia32_pcmpistrm128
__builtin_ia32_pd256_pd
__builtin_ia32_pd_pd256
__builtin_ia32_permdf256
__builtin_ia32_permdi256
__builtin_ia32_permti256
__builtin_ia32_permvarsf256
__builtin_ia32_permvarsi256
__builtin_ia32_pf2id
__builtin_ia32_pf2iw
__builtin_ia32_pfacc
__builtin_ia32_pfadd
__builtin_ia32_pfcmpeq
__builtin_ia32_pfcmpge
__builtin_ia32_pfcmpgt
__builtin_ia32_pfmax
__builtin_ia32_pfmin
__builtin_ia32_pfmul
__builtin_ia32_pfnacc
__builtin_ia32_pfpnacc
__builtin_ia32_pfrcp
__builtin_ia32_pfrcpit1
__builtin_ia32_pfrcpit2
__builtin_ia32_pfrsqrt
__builtin_ia32_pfsub
__builtin_ia32_pfsubr
__builtin_ia32_phaddd
__builtin_ia32_phaddd128
__builtin_ia32_phaddd256
__builtin_ia32_phaddsw
__builtin_ia32_phaddsw128
__builtin_ia32_phaddsw256
__builtin_ia32_phaddw
__builtin_ia32_phaddw128
__builtin_ia32_phaddw256
__builtin_ia32_phminposuw128
__builtin_ia32_phsubd
__builtin_ia32_phsubd128
__builtin_ia32_phsubd256
__builtin_ia32_phsubsw
__builtin_ia32_phsubsw128
__builtin_ia32_phsubsw256
__builtin_ia32_phsubw
__builtin_ia32_phsubw128
__builtin_ia32_phsubw256
__builtin_ia32_pi2fd
__builtin_ia32_pi2fw
__builtin_ia32_pmaddubsw
__builtin_ia32_pmaddubsw128
__builtin_ia32_pmaddubsw256
__builtin_ia32_pmaddwd128
__builtin_ia32_pmaddwd256
__builtin_ia32_pmaxsb128
__builtin_ia32_pmaxsb256
__builtin_ia32_pmaxsd128
__builtin_ia32_pmaxsd256
__builtin_ia32_pmaxsw
__builtin_ia32_pmaxsw128
__builtin_ia32_pmaxsw256
__builtin_ia32_pmaxub
__builtin_ia32_pmaxub128
__builtin_ia32_pmaxub256
__builtin_ia32_pmaxud128
__builtin_ia32_pmaxud256
__builtin_ia32_pmaxuw128
__builtin_ia32_pmaxuw256
__builtin_ia32_pminsb128
__builtin_ia32_pminsb256
__builtin_ia32_pminsd128
__builtin_ia32_pminsd256
__builtin_ia32_pminsw
__builtin_ia32_pminsw128
__builtin_ia32_pminsw256
__builtin_ia32_pminub
__builtin_ia32_pminub128
__builtin_ia32_pminub256
__builtin_ia32_pminud128
__builtin_ia32_pminud256
__builtin_ia32_pminuw128
__builtin_ia32_pminuw256
__builtin_ia32_pmovmskb
__builtin_ia32_pmovmskb128
__builtin_ia32_pmovmskb256
__builtin_ia32_pmovsxbd128
__builtin_ia32_pmovsxbd256
__builtin_ia32_pmovsxbq128
__builtin_ia32_pmovsxbq256
__builtin_ia32_pmovsxbw128
__builtin_ia32_pmovsxbw256
__builtin_ia32_pmovsxdq128
__builtin_ia32_pmovsxdq256
__builtin_ia32_pmovsxwd128
__builtin_ia32_pmovsxwd256
__builtin_ia32_pmovsxwq128
__builtin_ia32_pmovsxwq256
__builtin_ia32_pmovzxbd128
__builtin_ia32_pmovzxbd256
__builtin_ia32_pmovzxbq128
__builtin_ia32_pmovzxbq256
__builtin_ia32_pmovzxbw128
__builtin_ia32_pmovzxbw256
__builtin_ia32_pmovzxdq128
__builtin_ia32_pmovzxdq256
__builtin_ia32_pmovzxwd128
__builtin_ia32_pmovzxwd256
__builtin_ia32_pmovzxwq128
__builtin_ia32_pmovzxwq256
__builtin_ia32_pmuldq128
__builtin_ia32_pmuldq256
__builtin_ia32_pmulhrsw
__builtin_ia32_pmulhrsw128
__builtin_ia32_pmulhrsw256
__builtin_ia32_pmulhrw
__builtin_ia32_pmulhuw
__builtin_ia32_pmulhuw128
__builtin_ia32_pmulhuw256
__builtin_ia32_pmulhw
__builtin_ia32_pmulhw128
__builtin_ia32_pmulhw256
__builtin_ia32_pmulld128
__builtin_ia32_pmulld256
__builtin_ia32_pmullw
__builtin_ia32_pmullw128
__builtin_ia32_pmullw256
__builtin_ia32_pmuludq
__builtin_ia32_pmuludq128
__builtin_ia32_pmuludq256
__builtin_ia32_por
__builtin_ia32_por128
__builtin_ia32_por256
__builtin_ia32_ps256_ps
__builtin_ia32_ps_ps256
__builtin_ia32_psadbw
__builtin_ia32_psadbw128
__builtin_ia32_psadbw256
__builtin_ia32_pshufb
__builtin_ia32_pshufb128
__builtin_ia32_pshufb256
__builtin_ia32_pshufd
__builtin_ia32_pshufd256
__builtin_ia32_pshufhw
__builtin_ia32_pshufhw256
__builtin_ia32_pshuflw
__builtin_ia32_pshuflw256
__builtin_ia32_psignb
__builtin_ia32_psignb128
__builtin_ia32_psignb256
__builtin_ia32_psignd
__builtin_ia32_psignd128
__builtin_ia32_psignd256
__builtin_ia32_psignw
__builtin_ia32_psignw128
__builtin_ia32_psignw256
__builtin_ia32_pslld
__builtin_ia32_pslld128
__builtin_ia32_pslld256
__builtin_ia32_pslldi
__builtin_ia32_pslldi128
__builtin_ia32_pslldi256
__builtin_ia32_pslldqi128
__builtin_ia32_pslldqi256
__builtin_ia32_psllq
__builtin_ia32_psllq128
__builtin_ia32_psllq256
__builtin_ia32_psllqi
__builtin_ia32_psllqi128
__builtin_ia32_psllqi256
__builtin_ia32_psllv2di
__builtin_ia32_psllv4di
__builtin_ia32_psllv4si
__builtin_ia32_psllv8si
__builtin_ia32_psllw
__builtin_ia32_psllw128
__builtin_ia32_psllw256
__builtin_ia32_psllwi
__builtin_ia32_psllwi128
__builtin_ia32_psllwi256
__builtin_ia32_psrad
__builtin_ia32_psrad128
__builtin_ia32_psrad256
__builtin_ia32_psradi
__builtin_ia32_psradi128
__builtin_ia32_psradi256
__builtin_ia32_psrav4si
__builtin_ia32_psrav8si
__builtin_ia32_psraw
__builtin_ia32_psraw128
__builtin_ia32_psraw256
__builtin_ia32_psrawi
__builtin_ia32_psrawi128
__builtin_ia32_psrawi256
__builtin_ia32_psrld
__builtin_ia32_psrld128
__builtin_ia32_psrld256
__builtin_ia32_psrldi
__builtin_ia32_psrldi128
__builtin_ia32_psrldi256
__builtin_ia32_psrldqi128
__builtin_ia32_psrldqi256
__builtin_ia32_psrlq
__builtin_ia32_psrlq128
__builtin_ia32_psrlq256
__builtin_ia32_psrlqi
__builtin_ia32_psrlqi128
__builtin_ia32_psrlqi256
__builtin_ia32_psrlv2di
__builtin_ia32_psrlv4di
__builtin_ia32_psrlv4si
__builtin_ia32_psrlv8si
__builtin_ia32_psrlw
__builtin_ia32_psrlw128
__builtin_ia32_psrlw256
__builtin_ia32_psrlwi
__builtin_ia32_psrlwi128
__builtin_ia32_psrlwi256
__builtin_ia32_psubb
__builtin_ia32_psubb128
__builtin_ia32_psubb256
__builtin_ia32_psubd
__builtin_ia32_psubd128
__builtin_ia32_psubd256
__builtin_ia32_psubq
__builtin_ia32_psubq128
__builtin_ia32_psubq256
__builtin_ia32_psubsb
__builtin_ia32_psubsb256
__builtin_ia32_psubsw
__builtin_ia32_psubsw256
__builtin_ia32_psubusb
__builtin_ia32_psubusb256
__builtin_ia32_psubusw
__builtin_ia32_psubusw256
__builtin_ia32_psubw
__builtin_ia32_psubw128
__builtin_ia32_psubw256
__builtin_ia32_pswapdsf
__builtin_ia32_pswapdsi
__builtin_ia32_ptestc128
__builtin_ia32_ptestc256
__builtin_ia32_ptestnzc128
__builtin_ia32_ptestnzc256
__builtin_ia32_ptestz128
__builtin_ia32_ptestz256
__builtin_ia32_ptwrite32
__builtin_ia32_ptwrite64
__builtin_ia32_punpckhbw
__builtin_ia32_punpckhbw128
__builtin_ia32_punpckhbw256
__builtin_ia32_punpckhdq
__builtin_ia32_punpckhdq128
__builtin_ia32_punpckhdq256
__builtin_ia32_punpckhqdq128
__builtin_ia32_punpckhqdq256
__builtin_ia32_punpckhwd
__builtin_ia32_punpckhwd128
__builtin_ia32_punpckhwd256
__builtin_ia32_punpcklbw
__builtin_ia32_punpcklbw128
__builtin_ia32_punpcklbw256
__builtin_ia32_punpckldq
__builtin_ia32_punpckldq128
__builtin_ia32_punpckldq256
__builtin_ia32_punpcklqdq128
__builtin_ia32_punpcklqdq256
__builtin_ia32_punpcklwd
__builtin_ia32_punpcklwd128
__builtin_ia32_punpcklwd256
__builtin_ia32_pxor
__builtin_ia32_pxor128
__builtin_ia32_pxor256
__builtin_ia32_rcpps
__builtin_ia32_rcpps256
__builtin_ia32_rcpss
__builtin_ia32_rdfsbase32
__builtin_ia32_rdfsbase64
__builtin_ia32_rdgsbase32
__builtin_ia32_rdgsbase64
__builtin_ia32_rdpkru
__builtin_ia32_rdrand16_step
__builtin_ia32_rdrand32_step
__builtin_ia32_rdrand64_step
__builtin_ia32_rdsspd
__builtin_ia32_rdsspq
__builtin_ia32_roundpd
__builtin_ia32_roundpd256
__builtin_ia32_roundps
__builtin_ia32_roundps256
__builtin_ia32_roundsd
__builtin_ia32_roundss
__builtin_ia32_rsqrtps
__builtin_ia32_rsqrtps256
__builtin_ia32_rsqrtps_nr256
__builtin_ia32_rsqrtss
__builtin_ia32_rstorssp
__builtin_ia32_saveprevssp
__builtin_ia32_setssbsy
__builtin_ia32_sfence
__builtin_ia32_shufpd
__builtin_ia32_shufpd256
__builtin_ia32_shufps
__builtin_ia32_shufps256
__builtin_ia32_si256_si
__builtin_ia32_si_si256
__builtin_ia32_sqrtpd
__builtin_ia32_sqrtpd256
__builtin_ia32_sqrtps
__builtin_ia32_sqrtps256
__builtin_ia32_sqrtps_nr256
__builtin_ia32_sqrtsd
__builtin_ia32_sqrtss
__builtin_ia32_storedqu
__builtin_ia32_storedqu256
__builtin_ia32_storehps
__builtin_ia32_storelps
__builtin_ia32_storeupd
__builtin_ia32_storeupd256
__builtin_ia32_storeups
__builtin_ia32_storeups256
__builtin_ia32_subpd
__builtin_ia32_subpd256
__builtin_ia32_subps
__builtin_ia32_subps256
__builtin_ia32_subsd
__builtin_ia32_subss
__builtin_ia32_ucomieq
__builtin_ia32_ucomige
__builtin_ia32_ucomigt
__builtin_ia32_ucomile
__builtin_ia32_ucomilt
__builtin_ia32_ucomineq
__builtin_ia32_ucomisdeq
__builtin_ia32_ucomisdge
__builtin_ia32_ucomisdgt
__builtin_ia32_ucomisdle
__builtin_ia32_ucomisdlt
__builtin_ia32_ucomisdneq
__builtin_ia32_unpckhpd
__builtin_ia32_unpckhpd256
__builtin_ia32_unpckhps
__builtin_ia32_unpckhps256
__builtin_ia32_unpcklpd
__builtin_ia32_unpcklpd256
__builtin_ia32_unpcklps
__builtin_ia32_unpcklps256
__builtin_ia32_vbroadcastf128_pd256
__builtin_ia32_vbroadcastf128_ps256
__builtin_ia32_vbroadcastsd256
__builtin_ia32_vbroadcastsd_pd256
__builtin_ia32_vbroadcastsi256
__builtin_ia32_vbroadcastss
__builtin_ia32_vbroadcastss256
__builtin_ia32_vbroadcastss_ps
__builtin_ia32_vbroadcastss_ps256
__builtin_ia32_vec_ext_v16qi
__builtin_ia32_vec_ext_v2di
__builtin_ia32_vec_ext_v4sf
__builtin_ia32_vec_ext_v4si
__builtin_ia32_vec_set_v16qi
__builtin_ia32_vec_set_v2di
__builtin_ia32_vec_set_v4sf
__builtin_ia32_vec_set_v4si
__builtin_ia32_vextractf128_pd256
__builtin_ia32_vextractf128_ps256
__builtin_ia32_vextractf128_si256
__builtin_ia32_vfmaddpd
__builtin_ia32_vfmaddpd256
__builtin_ia32_vfmaddps
__builtin_ia32_vfmaddps256
__builtin_ia32_vfmaddsd
__builtin_ia32_vfmaddss
__builtin_ia32_vfmaddsubpd
__builtin_ia32_vfmaddsubpd256
__builtin_ia32_vfmaddsubps
__builtin_ia32_vfmaddsubps256
__builtin_ia32_vfmsubaddpd
__builtin_ia32_vfmsubaddpd256
__builtin_ia32_vfmsubaddps
__builtin_ia32_vfmsubaddps256
__builtin_ia32_vfmsubpd
__builtin_ia32_vfmsubpd256
__builtin_ia32_vfmsubps
__builtin_ia32_vfmsubps256
__builtin_ia32_vfmsubsd
__builtin_ia32_vfmsubss
__builtin_ia32_vfnmaddpd
__builtin_ia32_vfnmaddpd256
__builtin_ia32_vfnmaddps
__builtin_ia32_vfnmaddps256
__builtin_ia32_vfnmaddsd
__builtin_ia32_vfnmaddss
__builtin_ia32_vfnmsubpd
__builtin_ia32_vfnmsubpd256
__builtin_ia32_vfnmsubps
__builtin_ia32_vfnmsubps256
__builtin_ia32_vfnmsubsd
__builtin_ia32_vfnmsubss
__builtin_ia32_vfrczpd
__builtin_ia32_vfrczpd256
__builtin_ia32_vfrczps
__builtin_ia32_vfrczps256
__builtin_ia32_vfrczsd
__builtin_ia32_vfrczss
__builtin_ia32_vinsertf128_pd256
__builtin_ia32_vinsertf128_ps256
__builtin_ia32_vinsertf128_si256
__builtin_ia32_vpcmov
__builtin_ia32_vpcmov_v16hi256
__builtin_ia32_vpcmov_v16qi
__builtin_ia32_vpcmov_v2df
__builtin_ia32_vpcmov_v2di
__builtin_ia32_vpcmov_v32qi256
__builtin_ia32_vpcmov_v4df256
__builtin_ia32_vpcmov_v4di256
__builtin_ia32_vpcmov_v4sf
__builtin_ia32_vpcmov_v4si
__builtin_ia32_vpcmov_v8hi
__builtin_ia32_vpcmov_v8sf256
__builtin_ia32_vpcmov_v8si256
__builtin_ia32_vpcomeqb
__builtin_ia32_vpcomeqd
__builtin_ia32_vpcomeqq
__builtin_ia32_vpcomequb
__builtin_ia32_vpcomequd
__builtin_ia32_vpcomequq
__builtin_ia32_vpcomequw
__builtin_ia32_vpcomeqw
__builtin_ia32_vpcomfalseb
__builtin_ia32_vpcomfalsed
__builtin_ia32_vpcomfalseq
__builtin_ia32_vpcomfalseub
__builtin_ia32_vpcomfalseud
__builtin_ia32_vpcomfalseuq
__builtin_ia32_vpcomfalseuw
__builtin_ia32_vpcomfalsew
__builtin_ia32_vpcomgeb
__builtin_ia32_vpcomged
__builtin_ia32_vpcomgeq
__builtin_ia32_vpcomgeub
__builtin_ia32_vpcomgeud
__builtin_ia32_vpcomgeuq
__builtin_ia32_vpcomgeuw
__builtin_ia32_vpcomgew
__builtin_ia32_vpcomgtb
__builtin_ia32_vpcomgtd
__builtin_ia32_vpcomgtq
__builtin_ia32_vpcomgtub
__builtin_ia32_vpcomgtud
__builtin_ia32_vpcomgtuq
__builtin_ia32_vpcomgtuw
__builtin_ia32_vpcomgtw
__builtin_ia32_vpcomleb
__builtin_ia32_vpcomled
__builtin_ia32_vpcomleq
__builtin_ia32_vpcomleub
__builtin_ia32_vpcomleud
__builtin_ia32_vpcomleuq
__builtin_ia32_vpcomleuw
__builtin_ia32_vpcomlew
__builtin_ia32_vpcomltb
__builtin_ia32_vpcomltd
__builtin_ia32_vpcomltq
__builtin_ia32_vpcomltub
__builtin_ia32_vpcomltud
__builtin_ia32_vpcomltuq
__builtin_ia32_vpcomltuw
__builtin_ia32_vpcomltw
__builtin_ia32_vpcomneb
__builtin_ia32_vpcomned
__builtin_ia32_vpcomneq
__builtin_ia32_vpcomneub
__builtin_ia32_vpcomneud
__builtin_ia32_vpcomneuq
__builtin_ia32_vpcomneuw
__builtin_ia32_vpcomnew
__builtin_ia32_vpcomtrueb
__builtin_ia32_vpcomtrued
__builtin_ia32_vpcomtrueq
__builtin_ia32_vpcomtrueub
__builtin_ia32_vpcomtrueud
__builtin_ia32_vpcomtrueuq
__builtin_ia32_vpcomtrueuw
__builtin_ia32_vpcomtruew
__builtin_ia32_vperm2f128_pd256
__builtin_ia32_vperm2f128_ps256
__builtin_ia32_vperm2f128_si256
__builtin_ia32_vpermil2pd
__builtin_ia32_vpermil2pd256
__builtin_ia32_vpermil2ps
__builtin_ia32_vpermil2ps256
__builtin_ia32_vpermilpd
__builtin_ia32_vpermilpd256
__builtin_ia32_vpermilps
__builtin_ia32_vpermilps256
__builtin_ia32_vpermilvarpd
__builtin_ia32_vpermilvarpd256
__builtin_ia32_vpermilvarps
__builtin_ia32_vpermilvarps256
__builtin_ia32_vphaddbd
__builtin_ia32_vphaddbq
__builtin_ia32_vphaddbw
__builtin_ia32_vphadddq
__builtin_ia32_vphaddubd
__builtin_ia32_vphaddubq
__builtin_ia32_vphaddubw
__builtin_ia32_vphaddudq
__builtin_ia32_vphadduwd
__builtin_ia32_vphadduwq
__builtin_ia32_vphaddwd
__builtin_ia32_vphaddwq
__builtin_ia32_vphsubbw
__builtin_ia32_vphsubdq
__builtin_ia32_vphsubwd
__builtin_ia32_vpmacsdd
__builtin_ia32_vpmacsdqh
__builtin_ia32_vpmacsdql
__builtin_ia32_vpmacssdd
__builtin_ia32_vpmacssdqh
__builtin_ia32_vpmacssdql
__builtin_ia32_vpmacsswd
__builtin_ia32_vpmacssww
__builtin_ia32_vpmacswd
__builtin_ia32_vpmacsww
__builtin_ia32_vpmadcsswd
__builtin_ia32_vpmadcswd
__builtin_ia32_vpperm
__builtin_ia32_vprotb
__builtin_ia32_vprotd
__builtin_ia32_vprotq
__builtin_ia32_vprotw
__builtin_ia32_vpshab
__builtin_ia32_vpshad
__builtin_ia32_vpshaq
__builtin_ia32_vpshaw
__builtin_ia32_vpshlb
__builtin_ia32_vpshld
__builtin_ia32_vpshlq
__builtin_ia32_vpshlw
__builtin_ia32_vtestcpd
__builtin_ia32_vtestcpd256
__builtin_ia32_vtestcps
__builtin_ia32_vtestcps256
__builtin_ia32_vtestnzcpd
__builtin_ia32_vtestnzcpd256
__builtin_ia32_vtestnzcps
__builtin_ia32_vtestnzcps256
__builtin_ia32_vtestzpd
__builtin_ia32_vtestzpd256
__builtin_ia32_vtestzps
__builtin_ia32_vtestzps256
__builtin_ia32_vzeroall
__builtin_ia32_vzeroupper
__builtin_ia32_wrpkru
__builtin_ia32_wrssd
__builtin_ia32_wrssq
__builtin_ia32_wrussd
__builtin_ia32_wrussq
__builtin_ia32_xabort
__builtin_ia32_xbegin
__builtin_ia32_xend
__builtin_ia32_xorpd
__builtin_ia32_xorpd256
__builtin_ia32_xorps
__builtin_ia32_xorps256
__builtin_ia32_xrstor
__builtin_ia32_xrstor64
__builtin_ia32_xsave
__builtin_ia32_xsave64
__builtin_ia32_xsaveopt
__builtin_ia32_xsaveopt64
__builtin_ia32_xtest
__builtin_inf
__builtin_infd128
__builtin_infd32
__builtin_infd64
__builtin_inff
__builtin_inffn
__builtin_inffnx
__builtin_infl
__builtin_infq
__builtin_is_constant_evaluated
__builtin_iseqsig
__builtin_isfinite
__builtin_isgreater
__builtin_isgreaterequal
__builtin_isinf_sign
__builtin_isnan
__builtin_isnormal
__builtin_issignaling
__builtin_isunordered
__builtin_ldbio
__builtin_ldbuio
__builtin_ldex
__builtin_ldhio
__builtin_ldhuio
__builtin_ldsex
__builtin_ldwio
__builtin_longjmp
__builtin_loongarch_asrtgt_d
__builtin_loongarch_asrtle_d
__builtin_loongarch_break
__builtin_loongarch_cacop_d
__builtin_loongarch_cpucfg
__builtin_loongarch_crc_w_b_w
__builtin_loongarch_crc_w_d_w
__builtin_loongarch_crc_w_h_w
__builtin_loongarch_crc_w_w_w
__builtin_loongarch_crcc_w_b_w
__builtin_loongarch_crcc_w_d_w
__builtin_loongarch_crcc_w_h_w
__builtin_loongarch_crcc_w_w_w
__builtin_loongarch_csrrd_d
__builtin_loongarch_csrrd_w
__builtin_loongarch_csrwr_d
__builtin_loongarch_csrwr_w
__builtin_loongarch_csrxchg_d
__builtin_loongarch_csrxchg_w
__builtin_loongarch_dbar
__builtin_loongarch_frecipe_d
__builtin_loongarch_frecipe_s
__builtin_loongarch_frsqrte_d
__builtin_loongarch_frsqrte_s
__builtin_loongarch_ibar
__builtin_loongarch_iocsrrd_b
__builtin_loongarch_iocsrrd_d
__builtin_loongarch_iocsrrd_h
__builtin_loongarch_iocsrrd_w
__builtin_loongarch_iocsrwr_b
__builtin_loongarch_iocsrwr_d
__builtin_loongarch_iocsrwr_h
__builtin_loongarch_iocsrwr_w
__builtin_loongarch_lddir_d
__builtin_loongarch_ldpte_d
__builtin_loongarch_movfcsr2gr
__builtin_loongarch_movgr2fcsr
__builtin_loongarch_syscall
__builtin_lroundf
__builtin_malloc
__builtin_memcpy
__builtin_memcpy_chk
__builtin_memmove
__builtin_memset
__builtin_memset_chk
__builtin_mffs
__builtin_mffsl
__builtin_mips_abs_ps
__builtin_mips_absq_s_ph
__builtin_mips_absq_s_qb
__builtin_mips_absq_s_w
__builtin_mips_addq_ph
__builtin_mips_addq_s_ph
__builtin_mips_addq_s_w
__builtin_mips_addqh_ph
__builtin_mips_addqh_r_ph
__builtin_mips_addqh_r_w
__builtin_mips_addqh_w
__builtin_mips_addr_ps
__builtin_mips_addsc
__builtin_mips_addu_ph
__builtin_mips_addu_qb
__builtin_mips_addu_s_ph
__builtin_mips_addu_s_qb
__builtin_mips_adduh_qb
__builtin_mips_adduh_r_qb
__builtin_mips_addwc
__builtin_mips_all_c_cond_4s
__builtin_mips_all_c_cond_ps
__builtin_mips_all_c_eq_4s
__builtin_mips_all_c_eq_ps
__builtin_mips_all_cabs_cond_4s
__builtin_mips_all_cabs_cond_ps
__builtin_mips_alnv_ps
__builtin_mips_any_c_cond_4s
__builtin_mips_any_c_cond_ps
__builtin_mips_any_c_eq_4s
__builtin_mips_any_c_eq_ps
__builtin_mips_any_cabs_cond_4s
__builtin_mips_any_cabs_cond_ps
__builtin_mips_append
__builtin_mips_balign
__builtin_mips_bitrev
__builtin_mips_bposge32
__builtin_mips_cabs_cond_d
__builtin_mips_cabs_cond_s
__builtin_mips_cabs_eq_s
__builtin_mips_cache
__builtin_mips_cmp_eq_ph
__builtin_mips_cmp_le_ph
__builtin_mips_cmp_lt_ph
__builtin_mips_cmpgdu_eq_qb
__builtin_mips_cmpgdu_le_qb
__builtin_mips_cmpgdu_lt_qb
__builtin_mips_cmpgu_eq_qb
__builtin_mips_cmpgu_le_qb
__builtin_mips_cmpgu_lt_qb
__builtin_mips_cmpu_eq_qb
__builtin_mips_cmpu_le_qb
__builtin_mips_cmpu_lt_qb
__builtin_mips_cvt_ps_pw
__builtin_mips_cvt_ps_s
__builtin_mips_cvt_pw_ps
__builtin_mips_cvt_s_pl
__builtin_mips_cvt_s_pu
__builtin_mips_dpa_w_ph
__builtin_mips_dpaq_s_w_ph
__builtin_mips_dpaq_sa_l_w
__builtin_mips_dpaqx_s_w_ph
__builtin_mips_dpaqx_sa_w_ph
__builtin_mips_dpau_h_qbl
__builtin_mips_dpau_h_qbr
__builtin_mips_dpax_w_ph
__builtin_mips_dps_w_ph
__builtin_mips_dpsq_s_w_ph
__builtin_mips_dpsq_sa_l_w
__builtin_mips_dpsqx_s_w_ph
__builtin_mips_dpsqx_sa_w_ph
__builtin_mips_dpsu_h_qbl
__builtin_mips_dpsu_h_qbr
__builtin_mips_dpsx_w_ph
__builtin_mips_extp
__builtin_mips_extpdp
__builtin_mips_extr_r_w
__builtin_mips_extr_rs_w
__builtin_mips_extr_s_h
__builtin_mips_extr_w
__builtin_mips_get_fcsr
__builtin_mips_insv
__builtin_mips_lbux
__builtin_mips_ldx
__builtin_mips_lhx
__builtin_mips_lower_c_cond_ps
__builtin_mips_lower_c_eq_ps
__builtin_mips_lower_cabs_cond_ps
__builtin_mips_lower_cabs_eq_ps
__builtin_mips_lwx
__builtin_mips_madd
__builtin_mips_maddu
__builtin_mips_maq_s_w_phl
__builtin_mips_maq_s_w_phr
__builtin_mips_maq_sa_w_phl
__builtin_mips_maq_sa_w_phr
__builtin_mips_modsub
__builtin_mips_movf_c_cond_ps
__builtin_mips_movf_cabs_cond_ps
__builtin_mips_movt_c_cond_ps
__builtin_mips_movt_cabs_cond_ps
__builtin_mips_msub
__builtin_mips_msubu
__builtin_mips_mthlip
__builtin_mips_mul_ph
__builtin_mips_mul_s_ph
__builtin_mips_muleq_s_w_phl
__builtin_mips_muleq_s_w_phr
__builtin_mips_muleu_s_ph_qbl
__builtin_mips_muleu_s_ph_qbr
__builtin_mips_mulq_rs_ph
__builtin_mips_mulq_rs_w
__builtin_mips_mulq_s_ph
__builtin_mips_mulq_s_w
__builtin_mips_mulr_ps
__builtin_mips_mulsa_w_ph
__builtin_mips_mulsaq_s_w_ph
__builtin_mips_mult
__builtin_mips_multu
__builtin_mips_packrl_ph
__builtin_mips_pick_ph
__builtin_mips_pick_qb
__builtin_mips_pll_ps
__builtin_mips_plu_ps
__builtin_mips_preceq_w_phl
__builtin_mips_preceq_w_phr
__builtin_mips_precequ_ph_qbl
__builtin_mips_precequ_ph_qbla
__builtin_mips_precequ_ph_qbr
__builtin_mips_precequ_ph_qbra
__builtin_mips_preceu_ph_qbl
__builtin_mips_preceu_ph_qbla
__builtin_mips_preceu_ph_qbr
__builtin_mips_preceu_ph_qbra
__builtin_mips_precr_qb_ph
__builtin_mips_precr_sra_ph_w
__builtin_mips_precr_sra_r_ph_w
__builtin_mips_precrq_ph_w
__builtin_mips_precrq_qb_ph
__builtin_mips_precrq_rs_ph_w
__builtin_mips_precrqu_s_qb_ph
__builtin_mips_prepend
__builtin_mips_pul_ps
__builtin_mips_puu_ps
__builtin_mips_raddu_w_qb
__builtin_mips_rddsp
__builtin_mips_recip1_d
__builtin_mips_recip1_ps
__builtin_mips_recip1_s
__builtin_mips_recip2_d
__builtin_mips_recip2_ps
__builtin_mips_recip2_s
__builtin_mips_repl_ph
__builtin_mips_repl_qb
__builtin_mips_rsqrt1_d
__builtin_mips_rsqrt1_ps
__builtin_mips_rsqrt1_s
__builtin_mips_rsqrt2_d
__builtin_mips_rsqrt2_ps
__builtin_mips_rsqrt2_s
__builtin_mips_set_fcsr
__builtin_mips_shilo
__builtin_mips_shll_ph
__builtin_mips_shll_qb
__builtin_mips_shll_s_ph
__builtin_mips_shll_s_w
__builtin_mips_shra_ph
__builtin_mips_shra_qb
__builtin_mips_shra_r_ph
__builtin_mips_shra_r_qb
__builtin_mips_shra_r_w
__builtin_mips_shrl_ph
__builtin_mips_shrl_qb
__builtin_mips_subq_ph
__builtin_mips_subq_s_ph
__builtin_mips_subq_s_w
__builtin_mips_subqh_ph
__builtin_mips_subqh_r_ph
__builtin_mips_subqh_r_w
__builtin_mips_subqh_w
__builtin_mips_subu_ph
__builtin_mips_subu_qb
__builtin_mips_subu_s_ph
__builtin_mips_subu_s_qb
__builtin_mips_subuh_qb
__builtin_mips_subuh_r_qb
__builtin_mips_upper_c_cond_ps
__builtin_mips_upper_c_eq_ps
__builtin_mips_upper_cabs_cond_ps
__builtin_mips_upper_cabs_eq_ps
__builtin_mips_wrdsp
__builtin_mma_build_acc
__builtin_mma_disassemble_acc
__builtin_mma_pmxvbf16ger2
__builtin_mma_pmxvbf16ger2nn
__builtin_mma_pmxvbf16ger2np
__builtin_mma_pmxvbf16ger2pn
__builtin_mma_pmxvbf16ger2pp
__builtin_mma_pmxvf16ger2
__builtin_mma_pmxvf16ger2nn
__builtin_mma_pmxvf16ger2np
__builtin_mma_pmxvf16ger2pn
__builtin_mma_pmxvf16ger2pp
__builtin_mma_pmxvf32ger
__builtin_mma_pmxvf32gernn
__builtin_mma_pmxvf32gernp
__builtin_mma_pmxvf32gerpn
__builtin_mma_pmxvf32gerpp
__builtin_mma_pmxvf64ger
__builtin_mma_pmxvf64gernn
__builtin_mma_pmxvf64gernp
__builtin_mma_pmxvf64gerpn
__builtin_mma_pmxvf64gerpp
__builtin_mma_pmxvi16ger2
__builtin_mma_pmxvi16ger2pp
__builtin_mma_pmxvi16ger2s
__builtin_mma_pmxvi16ger2spp
__builtin_mma_pmxvi4ger8
__builtin_mma_pmxvi4ger8pp
__builtin_mma_pmxvi8ger4
__builtin_mma_pmxvi8ger4pp
__builtin_mma_pmxvi8ger4spp
__builtin_mma_xvbf16ger2
__builtin_mma_xvbf16ger2nn
__builtin_mma_xvbf16ger2np
__builtin_mma_xvbf16ger2pn
__builtin_mma_xvbf16ger2pp
__builtin_mma_xvf16ger2
__builtin_mma_xvf16ger2nn
__builtin_mma_xvf16ger2np
__builtin_mma_xvf16ger2pn
__builtin_mma_xvf16ger2pp
__builtin_mma_xvf32ger
__builtin_mma_xvf32gernn
__builtin_mma_xvf32gernp
__builtin_mma_xvf32gerpn
__builtin_mma_xvf32gerpp
__builtin_mma_xvf64ger
__builtin_mma_xvf64gernn
__builtin_mma_xvf64gernp
__builtin_mma_xvf64gerpn
__builtin_mma_xvf64gerpp
__builtin_mma_xvi16ger2
__builtin_mma_xvi16ger2pp
__builtin_mma_xvi16ger2s
__builtin_mma_xvi16ger2spp
__builtin_mma_xvi4ger8
__builtin_mma_xvi4ger8pp
__builtin_mma_xvi8ger4
__builtin_mma_xvi8ger4pp
__builtin_mma_xvi8ger4spp
__builtin_mma_xxmfacc
__builtin_mma_xxmtacc
__builtin_mma_xxsetaccz
__builtin_msa_
__builtin_msa_add_a_b
__builtin_msa_add_a_d
__builtin_msa_add_a_h
__builtin_msa_add_a_w
__builtin_msa_adds_a_b
__builtin_msa_adds_a_d
__builtin_msa_adds_a_h
__builtin_msa_adds_a_w
__builtin_msa_adds_s_b
__builtin_msa_adds_s_d
__builtin_msa_adds_s_h
__builtin_msa_adds_s_w
__builtin_msa_adds_u_b
__builtin_msa_adds_u_d
__builtin_msa_adds_u_h
__builtin_msa_adds_u_w
__builtin_msa_addv_b
__builtin_msa_addv_d
__builtin_msa_addv_h
__builtin_msa_addv_w
__builtin_msa_addvi_b
__builtin_msa_addvi_d
__builtin_msa_addvi_h
__builtin_msa_addvi_w
__builtin_msa_and_v
__builtin_msa_andi_b
__builtin_msa_asub_s_b
__builtin_msa_asub_s_d
__builtin_msa_asub_s_h
__builtin_msa_asub_s_w
__builtin_msa_asub_u_b
__builtin_msa_asub_u_d
__builtin_msa_asub_u_h
__builtin_msa_asub_u_w
__builtin_msa_ave_s_b
__builtin_msa_ave_s_d
__builtin_msa_ave_s_h
__builtin_msa_ave_s_w
__builtin_msa_ave_u_b
__builtin_msa_ave_u_d
__builtin_msa_ave_u_h
__builtin_msa_ave_u_w
__builtin_msa_aver_s_b
__builtin_msa_aver_s_d
__builtin_msa_aver_s_h
__builtin_msa_aver_s_w
__builtin_msa_aver_u_b
__builtin_msa_aver_u_d
__builtin_msa_aver_u_h
__builtin_msa_aver_u_w
__builtin_msa_bclr_b
__builtin_msa_bclr_d
__builtin_msa_bclr_h
__builtin_msa_bclr_w
__builtin_msa_bclri_b
__builtin_msa_bclri_d
__builtin_msa_bclri_h
__builtin_msa_bclri_w
__builtin_msa_binsl_b
__builtin_msa_binsl_d
__builtin_msa_binsl_h
__builtin_msa_binsl_w
__builtin_msa_binsli_b
__builtin_msa_binsli_d
__builtin_msa_binsli_h
__builtin_msa_binsli_w
__builtin_msa_binsr_b
__builtin_msa_binsr_d
__builtin_msa_binsr_h
__builtin_msa_binsr_w
__builtin_msa_binsri_b
__builtin_msa_binsri_d
__builtin_msa_binsri_h
__builtin_msa_binsri_w
__builtin_msa_bmnz_v
__builtin_msa_bmnzi_b
__builtin_msa_bmz_v
__builtin_msa_bmzi_b
__builtin_msa_bneg_b
__builtin_msa_bneg_d
__builtin_msa_bneg_h
__builtin_msa_bneg_w
__builtin_msa_bnegi_b
__builtin_msa_bnegi_d
__builtin_msa_bnegi_h
__builtin_msa_bnegi_w
__builtin_msa_bnz_b
__builtin_msa_bnz_d
__builtin_msa_bnz_h
__builtin_msa_bnz_v
__builtin_msa_bnz_w
__builtin_msa_bsel_v
__builtin_msa_bseli_b
__builtin_msa_bset_b
__builtin_msa_bset_d
__builtin_msa_bset_h
__builtin_msa_bset_w
__builtin_msa_bseti_b
__builtin_msa_bseti_d
__builtin_msa_bseti_h
__builtin_msa_bseti_w
__builtin_msa_bz_b
__builtin_msa_bz_d
__builtin_msa_bz_h
__builtin_msa_bz_v
__builtin_msa_bz_w
__builtin_msa_ceq_b
__builtin_msa_ceq_d
__builtin_msa_ceq_h
__builtin_msa_ceq_w
__builtin_msa_ceqi_b
__builtin_msa_ceqi_d
__builtin_msa_ceqi_h
__builtin_msa_ceqi_w
__builtin_msa_cfcmsa
__builtin_msa_cle_s_b
__builtin_msa_cle_s_d
__builtin_msa_cle_s_h
__builtin_msa_cle_s_w
__builtin_msa_cle_u_b
__builtin_msa_cle_u_d
__builtin_msa_cle_u_h
__builtin_msa_cle_u_w
__builtin_msa_clei_s_b
__builtin_msa_clei_s_d
__builtin_msa_clei_s_h
__builtin_msa_clei_s_w
__builtin_msa_clei_u_b
__builtin_msa_clei_u_d
__builtin_msa_clei_u_h
__builtin_msa_clei_u_w
__builtin_msa_clt_s_b
__builtin_msa_clt_s_d
__builtin_msa_clt_s_h
__builtin_msa_clt_s_w
__builtin_msa_clt_u_b
__builtin_msa_clt_u_d
__builtin_msa_clt_u_h
__builtin_msa_clt_u_w
__builtin_msa_clti_s_b
__builtin_msa_clti_s_d
__builtin_msa_clti_s_h
__builtin_msa_clti_s_w
__builtin_msa_clti_u_b
__builtin_msa_clti_u_d
__builtin_msa_clti_u_h
__builtin_msa_clti_u_w
__builtin_msa_copy_s_b
__builtin_msa_copy_s_d
__builtin_msa_copy_s_h
__builtin_msa_copy_s_w
__builtin_msa_copy_u_b
__builtin_msa_copy_u_d
__builtin_msa_copy_u_h
__builtin_msa_copy_u_w
__builtin_msa_ctcmsa
__builtin_msa_div_s_b
__builtin_msa_div_s_d
__builtin_msa_div_s_h
__builtin_msa_div_s_w
__builtin_msa_div_u_b
__builtin_msa_div_u_d
__builtin_msa_div_u_h
__builtin_msa_div_u_w
__builtin_msa_dotp_s_d
__builtin_msa_dotp_s_h
__builtin_msa_dotp_s_w
__builtin_msa_dotp_u_d
__builtin_msa_dotp_u_h
__builtin_msa_dotp_u_w
__builtin_msa_dpadd_s_d
__builtin_msa_dpadd_s_h
__builtin_msa_dpadd_s_w
__builtin_msa_dpadd_u_d
__builtin_msa_dpadd_u_h
__builtin_msa_dpadd_u_w
__builtin_msa_dpsub_s_d
__builtin_msa_dpsub_s_h
__builtin_msa_dpsub_s_w
__builtin_msa_dpsub_u_d
__builtin_msa_dpsub_u_h
__builtin_msa_dpsub_u_w
__builtin_msa_fadd_d
__builtin_msa_fadd_w
__builtin_msa_fcaf_d
__builtin_msa_fcaf_w
__builtin_msa_fceq_d
__builtin_msa_fceq_w
__builtin_msa_fclass_d
__builtin_msa_fclass_w
__builtin_msa_fcle_d
__builtin_msa_fcle_w
__builtin_msa_fclt_d
__builtin_msa_fclt_w
__builtin_msa_fcne_d
__builtin_msa_fcne_w
__builtin_msa_fcor_d
__builtin_msa_fcor_w
__builtin_msa_fcueq_d
__builtin_msa_fcueq_w
__builtin_msa_fcule_d
__builtin_msa_fcule_w
__builtin_msa_fcult_d
__builtin_msa_fcult_w
__builtin_msa_fcun_d
__builtin_msa_fcun_w
__builtin_msa_fcune_d
__builtin_msa_fcune_w
__builtin_msa_fdiv_d
__builtin_msa_fdiv_w
__builtin_msa_fexdo_h
__builtin_msa_fexdo_w
__builtin_msa_fexp2_d
__builtin_msa_fexp2_w
__builtin_msa_fexupl_d
__builtin_msa_fexupl_w
__builtin_msa_fexupr_d
__builtin_msa_fexupr_w
__builtin_msa_ffint_s_d
__builtin_msa_ffint_s_w
__builtin_msa_ffint_u_d
__builtin_msa_ffint_u_w
__builtin_msa_ffql_d
__builtin_msa_ffql_w
__builtin_msa_ffqr_d
__builtin_msa_ffqr_w
__builtin_msa_fill_b
__builtin_msa_fill_d
__builtin_msa_fill_h
__builtin_msa_fill_w
__builtin_msa_flog2_d
__builtin_msa_flog2_w
__builtin_msa_fmadd_d
__builtin_msa_fmadd_w
__builtin_msa_fmax_a_d
__builtin_msa_fmax_a_w
__builtin_msa_fmax_d
__builtin_msa_fmax_w
__builtin_msa_fmin_a_d
__builtin_msa_fmin_a_w
__builtin_msa_fmin_d
__builtin_msa_fmin_w
__builtin_msa_fmsub_d
__builtin_msa_fmsub_w
__builtin_msa_fmul_d
__builtin_msa_fmul_w
__builtin_msa_frcp_d
__builtin_msa_frcp_w
__builtin_msa_frint_d
__builtin_msa_frint_w
__builtin_msa_frsqrt_d
__builtin_msa_frsqrt_w
__builtin_msa_fsaf_d
__builtin_msa_fsaf_w
__builtin_msa_fseq_d
__builtin_msa_fseq_w
__builtin_msa_fsle_d
__builtin_msa_fsle_w
__builtin_msa_fslt_d
__builtin_msa_fslt_w
__builtin_msa_fsne_d
__builtin_msa_fsne_w
__builtin_msa_fsor_d
__builtin_msa_fsor_w
__builtin_msa_fsqrt_d
__builtin_msa_fsqrt_w
__builtin_msa_fsub_d
__builtin_msa_fsub_w
__builtin_msa_fsueq_d
__builtin_msa_fsueq_w
__builtin_msa_fsule_d
__builtin_msa_fsule_w
__builtin_msa_fsult_d
__builtin_msa_fsult_w
__builtin_msa_fsun_d
__builtin_msa_fsun_w
__builtin_msa_fsune_d
__builtin_msa_fsune_w
__builtin_msa_ftint_s_d
__builtin_msa_ftint_s_w
__builtin_msa_ftint_u_d
__builtin_msa_ftint_u_w
__builtin_msa_ftq_h
__builtin_msa_ftq_w
__builtin_msa_ftrunc_s_d
__builtin_msa_ftrunc_s_w
__builtin_msa_ftrunc_u_d
__builtin_msa_ftrunc_u_w
__builtin_msa_hadd_s_d
__builtin_msa_hadd_s_h
__builtin_msa_hadd_s_w
__builtin_msa_hadd_u_d
__builtin_msa_hadd_u_h
__builtin_msa_hadd_u_w
__builtin_msa_hsub_s_d
__builtin_msa_hsub_s_h
__builtin_msa_hsub_s_w
__builtin_msa_hsub_u_d
__builtin_msa_hsub_u_h
__builtin_msa_hsub_u_w
__builtin_msa_ilvev_b
__builtin_msa_ilvev_d
__builtin_msa_ilvev_h
__builtin_msa_ilvev_w
__builtin_msa_ilvl_b
__builtin_msa_ilvl_d
__builtin_msa_ilvl_h
__builtin_msa_ilvl_w
__builtin_msa_ilvod_b
__builtin_msa_ilvod_d
__builtin_msa_ilvod_h
__builtin_msa_ilvod_w
__builtin_msa_ilvr_b
__builtin_msa_ilvr_d
__builtin_msa_ilvr_h
__builtin_msa_ilvr_w
__builtin_msa_insert_b
__builtin_msa_insert_d
__builtin_msa_insert_h
__builtin_msa_insert_w
__builtin_msa_insve_b
__builtin_msa_insve_d
__builtin_msa_insve_h
__builtin_msa_insve_w
__builtin_msa_ld_b
__builtin_msa_ld_d
__builtin_msa_ld_h
__builtin_msa_ld_w
__builtin_msa_ldi_b
__builtin_msa_ldi_d
__builtin_msa_ldi_h
__builtin_msa_ldi_w
__builtin_msa_madd_q_h
__builtin_msa_madd_q_w
__builtin_msa_maddr_q_h
__builtin_msa_maddr_q_w
__builtin_msa_maddv_b
__builtin_msa_maddv_d
__builtin_msa_maddv_h
__builtin_msa_maddv_w
__builtin_msa_max_a_b
__builtin_msa_max_a_d
__builtin_msa_max_a_h
__builtin_msa_max_a_w
__builtin_msa_max_s_b
__builtin_msa_max_s_d
__builtin_msa_max_s_h
__builtin_msa_max_s_w
__builtin_msa_max_u_b
__builtin_msa_max_u_d
__builtin_msa_max_u_h
__builtin_msa_max_u_w
__builtin_msa_maxi_s_b
__builtin_msa_maxi_s_d
__builtin_msa_maxi_s_h
__builtin_msa_maxi_s_w
__builtin_msa_maxi_u_b
__builtin_msa_maxi_u_d
__builtin_msa_maxi_u_h
__builtin_msa_maxi_u_w
__builtin_msa_min_a_b
__builtin_msa_min_a_d
__builtin_msa_min_a_h
__builtin_msa_min_a_w
__builtin_msa_min_s_b
__builtin_msa_min_s_d
__builtin_msa_min_s_h
__builtin_msa_min_s_w
__builtin_msa_min_u_b
__builtin_msa_min_u_d
__builtin_msa_min_u_h
__builtin_msa_min_u_w
__builtin_msa_mini_s_b
__builtin_msa_mini_s_d
__builtin_msa_mini_s_h
__builtin_msa_mini_s_w
__builtin_msa_mini_u_b
__builtin_msa_mini_u_d
__builtin_msa_mini_u_h
__builtin_msa_mini_u_w
__builtin_msa_mod_s_b
__builtin_msa_mod_s_d
__builtin_msa_mod_s_h
__builtin_msa_mod_s_w
__builtin_msa_mod_u_b
__builtin_msa_mod_u_d
__builtin_msa_mod_u_h
__builtin_msa_mod_u_w
__builtin_msa_move_v
__builtin_msa_msub_q_h
__builtin_msa_msub_q_w
__builtin_msa_msubr_q_h
__builtin_msa_msubr_q_w
__builtin_msa_msubv_b
__builtin_msa_msubv_d
__builtin_msa_msubv_h
__builtin_msa_msubv_w
__builtin_msa_mul_q_h
__builtin_msa_mul_q_w
__builtin_msa_mulr_q_h
__builtin_msa_mulr_q_w
__builtin_msa_mulv_b
__builtin_msa_mulv_d
__builtin_msa_mulv_h
__builtin_msa_mulv_w
__builtin_msa_nloc_b
__builtin_msa_nloc_d
__builtin_msa_nloc_h
__builtin_msa_nloc_w
__builtin_msa_nlzc_b
__builtin_msa_nlzc_d
__builtin_msa_nlzc_h
__builtin_msa_nlzc_w
__builtin_msa_nor_v
__builtin_msa_nori_b
__builtin_msa_or_v
__builtin_msa_ori_b
__builtin_msa_pckev_b
__builtin_msa_pckev_d
__builtin_msa_pckev_h
__builtin_msa_pckev_w
__builtin_msa_pckod_b
__builtin_msa_pckod_d
__builtin_msa_pckod_h
__builtin_msa_pckod_w
__builtin_msa_pcnt_b
__builtin_msa_pcnt_d
__builtin_msa_pcnt_h
__builtin_msa_pcnt_w
__builtin_msa_sat_s_b
__builtin_msa_sat_s_d
__builtin_msa_sat_s_h
__builtin_msa_sat_s_w
__builtin_msa_sat_u_b
__builtin_msa_sat_u_d
__builtin_msa_sat_u_h
__builtin_msa_sat_u_w
__builtin_msa_shf_b
__builtin_msa_shf_h
__builtin_msa_shf_w
__builtin_msa_sld_b
__builtin_msa_sld_d
__builtin_msa_sld_h
__builtin_msa_sld_w
__builtin_msa_sldi_b
__builtin_msa_sldi_d
__builtin_msa_sldi_h
__builtin_msa_sldi_w
__builtin_msa_sll_b
__builtin_msa_sll_d
__builtin_msa_sll_h
__builtin_msa_sll_w
__builtin_msa_slli_b
__builtin_msa_slli_d
__builtin_msa_slli_h
__builtin_msa_slli_w
__builtin_msa_splat_b
__builtin_msa_splat_d
__builtin_msa_splat_h
__builtin_msa_splat_w
__builtin_msa_splati_b
__builtin_msa_splati_d
__builtin_msa_splati_h
__builtin_msa_splati_w
__builtin_msa_sra_b
__builtin_msa_sra_d
__builtin_msa_sra_h
__builtin_msa_sra_w
__builtin_msa_srai_b
__builtin_msa_srai_d
__builtin_msa_srai_h
__builtin_msa_srai_w
__builtin_msa_srar_b
__builtin_msa_srar_d
__builtin_msa_srar_h
__builtin_msa_srar_w
__builtin_msa_srari_b
__builtin_msa_srari_d
__builtin_msa_srari_h
__builtin_msa_srari_w
__builtin_msa_srl_b
__builtin_msa_srl_d
__builtin_msa_srl_h
__builtin_msa_srl_w
__builtin_msa_srli_b
__builtin_msa_srli_d
__builtin_msa_srli_h
__builtin_msa_srli_w
__builtin_msa_srlr_b
__builtin_msa_srlr_d
__builtin_msa_srlr_h
__builtin_msa_srlr_w
__builtin_msa_srlri_b
__builtin_msa_srlri_d
__builtin_msa_srlri_h
__builtin_msa_srlri_w
__builtin_msa_st_b
__builtin_msa_st_d
__builtin_msa_st_h
__builtin_msa_st_w
__builtin_msa_subs_s_b
__builtin_msa_subs_s_d
__builtin_msa_subs_s_h
__builtin_msa_subs_s_w
__builtin_msa_subs_u_b
__builtin_msa_subs_u_d
__builtin_msa_subs_u_h
__builtin_msa_subs_u_w
__builtin_msa_subsus_u_b
__builtin_msa_subsus_u_d
__builtin_msa_subsus_u_h
__builtin_msa_subsus_u_w
__builtin_msa_subsuu_s_b
__builtin_msa_subsuu_s_d
__builtin_msa_subsuu_s_h
__builtin_msa_subsuu_s_w
__builtin_msa_subv_b
__builtin_msa_subv_d
__builtin_msa_subv_h
__builtin_msa_subv_w
__builtin_msa_subvi_b
__builtin_msa_subvi_d
__builtin_msa_subvi_h
__builtin_msa_subvi_w
__builtin_msa_vshf_b
__builtin_msa_vshf_d
__builtin_msa_vshf_h
__builtin_msa_vshf_w
__builtin_msa_xor_v
__builtin_msa_xori_b
__builtin_mtfsb0
__builtin_mtfsb1
__builtin_mtfsf
__builtin_mul_overflow
__builtin_mul_overflow_p
__builtin_mulf128_round_to_odd
__builtin_nan
__builtin_nand128
__builtin_nand32
__builtin_nand64
__builtin_nanf
__builtin_nanfn
__builtin_nanfnx
__builtin_nanl
__builtin_nanq
__builtin_nans
__builtin_nansd128
__builtin_nansd32
__builtin_nansd64
__builtin_nansf
__builtin_nansfn
__builtin_nansfnx
__builtin_nansl
__builtin_nansq
__builtin_nds32_isb
__builtin_nds32_isync
__builtin_nds32_mfsr
__builtin_nds32_mfusr
__builtin_nds32_mtsr
__builtin_nds32_mtusr
__builtin_nds32_setgie_dis
__builtin_nds32_setgie_en
__builtin_next_arg
__builtin_non_tx_store
__builtin_nvptx_brev
__builtin_nvptx_brevll
__builtin_object_size
__builtin_offsetof
__builtin_pack_dec128
__builtin_pack_ibm128
__builtin_pack_longdouble
__builtin_pack_vector_int128
__builtin_parity
__builtin_parityg
__builtin_parityl
__builtin_parityll
__builtin_pdepd
__builtin_pextd
__builtin_popcount
__builtin_popcountg
__builtin_popcountl
__builtin_popcountll
__builtin_powi
__builtin_powif
__builtin_powil
__builtin_ppc_get_timebase
__builtin_ppc_mftb
__builtin_prefetch
__builtin_preserve_access_index
__builtin_preserve_enum_value
__builtin_preserve_field_info
__builtin_preserve_type_info
__builtin_printf
__builtin_printf_unlocked
__builtin_putc
__builtin_putc_unlocked
__builtin_putchar
__builtin_putchar_unlocked
__builtin_puts
__builtin_puts_unlocked
__builtin_rdctl
__builtin_rdprs
__builtin_read16
__builtin_read32
__builtin_read64
__builtin_read8
__builtin_realloc
__builtin_recipdiv
__builtin_recipdivf
__builtin_return
__builtin_return_address
__builtin_riscv_cv_alu_addN
__builtin_riscv_cv_alu_addRN
__builtin_riscv_cv_alu_adduN
__builtin_riscv_cv_alu_adduRN
__builtin_riscv_cv_alu_clip
__builtin_riscv_cv_alu_clipu
__builtin_riscv_cv_alu_extbs
__builtin_riscv_cv_alu_extbz
__builtin_riscv_cv_alu_exths
__builtin_riscv_cv_alu_exthz
__builtin_riscv_cv_alu_max
__builtin_riscv_cv_alu_maxu
__builtin_riscv_cv_alu_min
__builtin_riscv_cv_alu_minu
__builtin_riscv_cv_alu_slet
__builtin_riscv_cv_alu_sletu
__builtin_riscv_cv_alu_subN
__builtin_riscv_cv_alu_subRN
__builtin_riscv_cv_alu_subuN
__builtin_riscv_cv_alu_subuRN
__builtin_riscv_cv_elw_elw
__builtin_riscv_cv_mac_mac
__builtin_riscv_cv_mac_machhsN
__builtin_riscv_cv_mac_machhsRN
__builtin_riscv_cv_mac_machhuN
__builtin_riscv_cv_mac_machhuRN
__builtin_riscv_cv_mac_macsN
__builtin_riscv_cv_mac_macsRN
__builtin_riscv_cv_mac_macuN
__builtin_riscv_cv_mac_macuRN
__builtin_riscv_cv_mac_msu
__builtin_riscv_cv_mac_mulhhsN
__builtin_riscv_cv_mac_mulhhsRN
__builtin_riscv_cv_mac_mulhhuN
__builtin_riscv_cv_mac_mulhhuRN
__builtin_riscv_cv_mac_mulsN
__builtin_riscv_cv_mac_mulsRN
__builtin_riscv_cv_mac_muluN
__builtin_riscv_cv_mac_muluRN
__builtin_riscv_cv_simd_abs_b
__builtin_riscv_cv_simd_abs_h
__builtin_riscv_cv_simd_add_b
__builtin_riscv_cv_simd_add_h
__builtin_riscv_cv_simd_add_sc_b
__builtin_riscv_cv_simd_add_sc_h
__builtin_riscv_cv_simd_and_b
__builtin_riscv_cv_simd_and_h
__builtin_riscv_cv_simd_and_sc_b
__builtin_riscv_cv_simd_and_sc_h
__builtin_riscv_cv_simd_avg_b
__builtin_riscv_cv_simd_avg_h
__builtin_riscv_cv_simd_avg_sc_b
__builtin_riscv_cv_simd_avg_sc_h
__builtin_riscv_cv_simd_avgu_b
__builtin_riscv_cv_simd_avgu_h
__builtin_riscv_cv_simd_avgu_sc_b
__builtin_riscv_cv_simd_avgu_sc_h
__builtin_riscv_cv_simd_cmpeq_b
__builtin_riscv_cv_simd_cmpeq_h
__builtin_riscv_cv_simd_cmpeq_sc_b
__builtin_riscv_cv_simd_cmpeq_sc_h
__builtin_riscv_cv_simd_cmpge_b
__builtin_riscv_cv_simd_cmpge_h
__builtin_riscv_cv_simd_cmpge_sc_b
__builtin_riscv_cv_simd_cmpge_sc_h
__builtin_riscv_cv_simd_cmpgeu_b
__builtin_riscv_cv_simd_cmpgeu_h
__builtin_riscv_cv_simd_cmpgeu_sc_b
__builtin_riscv_cv_simd_cmpgeu_sc_h
__builtin_riscv_cv_simd_cmpgt_b
__builtin_riscv_cv_simd_cmpgt_h
__builtin_riscv_cv_simd_cmpgt_sc_b
__builtin_riscv_cv_simd_cmpgt_sc_h
__builtin_riscv_cv_simd_cmpgtu_b
__builtin_riscv_cv_simd_cmpgtu_h
__builtin_riscv_cv_simd_cmpgtu_sc_b
__builtin_riscv_cv_simd_cmpgtu_sc_h
__builtin_riscv_cv_simd_cmple_b
__builtin_riscv_cv_simd_cmple_h
__builtin_riscv_cv_simd_cmple_sc_b
__builtin_riscv_cv_simd_cmple_sc_h
__builtin_riscv_cv_simd_cmpleu_b
__builtin_riscv_cv_simd_cmpleu_h
__builtin_riscv_cv_simd_cmpleu_sc_b
__builtin_riscv_cv_simd_cmpleu_sc_h
__builtin_riscv_cv_simd_cmplt_b
__builtin_riscv_cv_simd_cmplt_h
__builtin_riscv_cv_simd_cmplt_sc_b
__builtin_riscv_cv_simd_cmplt_sc_h
__builtin_riscv_cv_simd_cmpltu_b
__builtin_riscv_cv_simd_cmpltu_h
__builtin_riscv_cv_simd_cmpltu_sc_b
__builtin_riscv_cv_simd_cmpltu_sc_h
__builtin_riscv_cv_simd_cmpne_b
__builtin_riscv_cv_simd_cmpne_h
__builtin_riscv_cv_simd_cmpne_sc_b
__builtin_riscv_cv_simd_cmpne_sc_h
__builtin_riscv_cv_simd_cplxconj
__builtin_riscv_cv_simd_cplxmul_i
__builtin_riscv_cv_simd_cplxmul_r
__builtin_riscv_cv_simd_dotsp_b
__builtin_riscv_cv_simd_dotsp_h
__builtin_riscv_cv_simd_dotsp_sc_b
__builtin_riscv_cv_simd_dotsp_sc_h
__builtin_riscv_cv_simd_dotup_b
__builtin_riscv_cv_simd_dotup_h
__builtin_riscv_cv_simd_dotup_sc_b
__builtin_riscv_cv_simd_dotup_sc_h
__builtin_riscv_cv_simd_dotusp_b
__builtin_riscv_cv_simd_dotusp_h
__builtin_riscv_cv_simd_dotusp_sc_b
__builtin_riscv_cv_simd_dotusp_sc_h
__builtin_riscv_cv_simd_extract_b
__builtin_riscv_cv_simd_extract_h
__builtin_riscv_cv_simd_extractu_b
__builtin_riscv_cv_simd_extractu_h
__builtin_riscv_cv_simd_insert_b
__builtin_riscv_cv_simd_insert_h
__builtin_riscv_cv_simd_max_b
__builtin_riscv_cv_simd_max_h
__builtin_riscv_cv_simd_max_sc_b
__builtin_riscv_cv_simd_max_sc_h
__builtin_riscv_cv_simd_maxu_b
__builtin_riscv_cv_simd_maxu_h
__builtin_riscv_cv_simd_maxu_sc_b
__builtin_riscv_cv_simd_maxu_sc_h
__builtin_riscv_cv_simd_min_b
__builtin_riscv_cv_simd_min_h
__builtin_riscv_cv_simd_min_sc_b
__builtin_riscv_cv_simd_min_sc_h
__builtin_riscv_cv_simd_minu_b
__builtin_riscv_cv_simd_minu_h
__builtin_riscv_cv_simd_minu_sc_b
__builtin_riscv_cv_simd_minu_sc_h
__builtin_riscv_cv_simd_or_b
__builtin_riscv_cv_simd_or_h
__builtin_riscv_cv_simd_or_sc_b
__builtin_riscv_cv_simd_or_sc_h
__builtin_riscv_cv_simd_packhi_b
__builtin_riscv_cv_simd_packhi_h
__builtin_riscv_cv_simd_packlo_b
__builtin_riscv_cv_simd_packlo_h
__builtin_riscv_cv_simd_sdotsp_b
__builtin_riscv_cv_simd_sdotsp_h
__builtin_riscv_cv_simd_sdotsp_sc_b
__builtin_riscv_cv_simd_sdotsp_sc_h
__builtin_riscv_cv_simd_sdotup_b
__builtin_riscv_cv_simd_sdotup_h
__builtin_riscv_cv_simd_sdotup_sc_b
__builtin_riscv_cv_simd_sdotup_sc_h
__builtin_riscv_cv_simd_sdotusp_b
__builtin_riscv_cv_simd_sdotusp_h
__builtin_riscv_cv_simd_sdotusp_sc_b
__builtin_riscv_cv_simd_sdotusp_sc_h
__builtin_riscv_cv_simd_shuffle2_b
__builtin_riscv_cv_simd_shuffle2_h
__builtin_riscv_cv_simd_shuffle_b
__builtin_riscv_cv_simd_shuffle_h
__builtin_riscv_cv_simd_shuffle_sci_h
__builtin_riscv_cv_simd_shufflei0_sci_b
__builtin_riscv_cv_simd_shufflei1_sci_b
__builtin_riscv_cv_simd_shufflei2_sci_b
__builtin_riscv_cv_simd_shufflei3_sci_b
__builtin_riscv_cv_simd_sll_b
__builtin_riscv_cv_simd_sll_h
__builtin_riscv_cv_simd_sll_sc_b
__builtin_riscv_cv_simd_sll_sc_h
__builtin_riscv_cv_simd_sra_b
__builtin_riscv_cv_simd_sra_h
__builtin_riscv_cv_simd_sra_sc_b
__builtin_riscv_cv_simd_sra_sc_h
__builtin_riscv_cv_simd_srl_b
__builtin_riscv_cv_simd_srl_h
__builtin_riscv_cv_simd_srl_sc_b
__builtin_riscv_cv_simd_srl_sc_h
__builtin_riscv_cv_simd_sub_b
__builtin_riscv_cv_simd_sub_h
__builtin_riscv_cv_simd_sub_sc_b
__builtin_riscv_cv_simd_sub_sc_h
__builtin_riscv_cv_simd_subrotmj
__builtin_riscv_cv_simd_xor_b
__builtin_riscv_cv_simd_xor_h
__builtin_riscv_cv_simd_xor_sc_b
__builtin_riscv_cv_simd_xor_sc_h
__builtin_riscv_pause
__builtin_rs6000_speculation_barrier
__builtin_rsqrt
__builtin_rsqrtf
__builtin_rx_brk
__builtin_rx_clrpsw
__builtin_rx_int
__builtin_rx_machi
__builtin_rx_maclo
__builtin_rx_mulhi
__builtin_rx_mullo
__builtin_rx_mvfachi
__builtin_rx_mvfacmi
__builtin_rx_mvfc
__builtin_rx_mvtachi
__builtin_rx_mvtaclo
__builtin_rx_mvtc
__builtin_rx_mvtipl
__builtin_rx_racw
__builtin_rx_revw
__builtin_rx_rmpa
__builtin_rx_round
__builtin_rx_sat
__builtin_rx_setpsw
__builtin_rx_wait
__builtin_sadd_overflow
__builtin_saddl_overflow
__builtin_saddll_overflow
__builtin_set_fpscr_drn
__builtin_set_fpscr_rn
__builtin_set_texasr
__builtin_set_texasru
__builtin_set_tfhar
__builtin_set_tfiar
__builtin_set_thread_pointer
__builtin_setjmp
__builtin_sh_get_fpscr
__builtin_sh_set_fpscr
__builtin_shuffle
__builtin_shufflevector
__builtin_signbit
__builtin_signbitf
__builtin_signbitl
__builtin_smul_overflow
__builtin_smull_overflow
__builtin_smulll_overflow
__builtin_speculation_safe_copy
__builtin_speculation_safe_value
__builtin_sqrtf128
__builtin_sqrtf128_round_to_odd
__builtin_ssub_overflow
__builtin_ssubl_overflow
__builtin_ssubll_overflow
__builtin_stack_address
__builtin_stack_restore
__builtin_stack_save
__builtin_stbio
__builtin_stdc_bit_ceil
__builtin_stdc_bit_floor
__builtin_stdc_bit_width
__builtin_stdc_count_ones
__builtin_stdc_count_zeros
__builtin_stdc_first_leading_one
__builtin_stdc_first_leading_zero
__builtin_stdc_first_trailing_one
__builtin_stdc_first_trailing_zero
__builtin_stdc_has_single_bit
__builtin_stdc_leading_ones
__builtin_stdc_leading_zeros
__builtin_stdc_trailing_ones
__builtin_stdc_trailing_zeros
__builtin_stex
__builtin_sthio
__builtin_strchr
__builtin_strcpy
__builtin_strcpy_chk
__builtin_strlen
__builtin_stsex
__builtin_stwio
__builtin_sub_overflow
__builtin_sub_overflow_p
__builtin_subc
__builtin_subcl
__builtin_subcll
__builtin_subf128_round_to_odd
__builtin_sync
__builtin_tabort
__builtin_tabortdc
__builtin_tabortdci
__builtin_tabortwc
__builtin_tabortwci
__builtin_tbegin
__builtin_tbegin_nofloat
__builtin_tbegin_retry
__builtin_tbegin_retry_nofloat
__builtin_tbeginc
__builtin_tcheck
__builtin_tend
__builtin_tendall
__builtin_tgmath
__builtin_thread_pointer
__builtin_trap
__builtin_trechkpt
__builtin_treclaim
__builtin_tresume
__builtin_truncf128_round_to_odd
__builtin_tsr
__builtin_tsuspend
__builtin_ttest
__builtin_tx_assist
__builtin_tx_nesting_depth
__builtin_types_compatible_p
__builtin_uadd_overflow
__builtin_uaddl_overflow
__builtin_uaddll_overflow
__builtin_umul_overflow
__builtin_umull_overflow
__builtin_umulll_overflow
__builtin_unpack_dec128
__builtin_unpack_ibm128
__builtin_unpack_longdouble
__builtin_unpack_vector_int128
__builtin_unreachable
__builtin_usub_overflow
__builtin_usubl_overflow
__builtin_usubll_overflow
__builtin_va_arg
__builtin_va_arg_pack
__builtin_va_arg_pack_len
__builtin_va_copy
__builtin_va_end
__builtin_va_list
__builtin_va_start
__builtin_vfprintf
__builtin_vprintf
__builtin_vsx_build_pair
__builtin_vsx_disassemble_pair
__builtin_vsx_lxvp
__builtin_vsx_stxvp
__builtin_vsx_xvcvbf16spn
__builtin_vsx_xvcvspbf16
__builtin_wrctl
__builtin_write16
__builtin_write32
__builtin_write64
__builtin_write8
__builtin_wrpie
__conceal
__dll_import
__expropriate
__has_feature
__has_include
__has_nothrow_assign
__has_nothrow_constructor
__has_nothrow_copy
__has_trivial_assign
__has_trivial_constructor
__has_trivial_copy
__has_trivial_destructor
__has_virtual_destructor
__integer_pack
__is_abstract
__is_base_of
__is_class
__is_empty
__is_enum
__is_literal_type
__is_pod
__is_polymorphic
__is_same
__is_standard_layout
__is_trivial
__is_union
__notice
__shfl
__shfl_down
__shfl_down_sync
__shfl_sync
__shfl_up_sync
__shfl_xor
__shfl_xor_sync
__static_yoink
__strong_reference
__target_clones
__underlying_type
__veil
__vex
__weak_reference
__yoink
static_assert
