# Copyright (c) 2017 Christian Taedcke
# Copyright (c) 2018 Gil Benkoe
# SPDX-License-Identifier: Apache-2.0

rsource "*/Kconfig"

config SILABS_SHELL
	bool
	depends on SHELL
	help
	  Hidden option that enables the "silabs" shell command namespace.
	  Selected by any Silicon Labs SoC feature that registers a subcommand.

if SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2

config SOC_GECKO_HAS_RADIO
	bool
	help
	  If enabled, indicates that the SoC has a Radio PHY.

config SOC_GECKO_USE_RAIL
	bool "Use RAIL (Radio Abstraction Interface Layer)"
	depends on SOC_GECKO_HAS_RADIO
	select SILABS_SISDK_LDMA
	select SILABS_SISDK_TIMER if BT_CHANNEL_SOUNDING
	help
	  RAIL (Radio Abstraction Interface Layer) is a library needed to use the EFR radio
	  hardware. This option enable the proper set of features to allow to properly compile
	  with the RAIL blob.

config SOC_GECKO_CUSTOM_RADIO_PHY
	bool "Use RAIL for custom radio phy packet sending and receiving"
	depends on SOC_GECKO_HAS_RADIO
	select SOC_GECKO_USE_RAIL
	help
	  If enabled, RAIL can be used for user generated custom radio phy
	  management, sending and receiving packets on radio phy. User has
	  to provide the radio_config.c and radio_config.h files for the phy.

endif # SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2

if SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1

config SILABS_GECKO_EMU_DCDC
	bool "SoC DC/DC regulator"
	select SILABS_GECKO_EMU
	help
	  Enable the on chip DC/DC regulator

choice SILABS_GECKO_EMU_DCDC_MODE
	prompt "DC/DC mode"
	depends on SILABS_GECKO_EMU_DCDC
	help
	  Select power configuration mode of the on chip DC/DC converter.

	config SILABS_GECKO_EMU_DCDC_MODE_UNCONFIGURED
		bool "Initial / Unconfigured"

	config SILABS_GECKO_EMU_DCDC_MODE_ON
		bool "DC/DC On"

	config SILABS_GECKO_EMU_DCDC_MODE_OFF
		bool "DC/DC Off"

	config SILABS_GECKO_EMU_DCDC_MODE_BYPASS
		bool "Bypass"
endchoice

config SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
	bool
	help
	  If enabled, indicates that SoC allows to configure individual pin
	  locations. This is supported by e.g. efr32fg1p, efr32mg12p series.
	  If disabled, indicates that pin locations are configured in groups.
	  This is supported by e.g. efm32hg, efm32wg series.

config SOC_GECKO_HAS_ERRATA_RTCC_E201
	bool
	help
	  Set if the SoC is affected by errata RTCC_E201:
	  "When the RTCC is configured with a prescaler, the CCV1 top value enable
	  feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter
	  when RTCC_CNT is equal to RTCC_CC1_CCV, as intended."

endif # SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1
