# Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_ESP32P4
	select RISCV
	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
	select DYNAMIC_INTERRUPTS if SOC_ESP32P4_HPCORE
	select CLOCK_CONTROL if SOC_ESP32P4_HPCORE
	select PINCTRL if SOC_ESP32P4_HPCORE
	select HAS_ESPRESSIF_HAL
	select CPU_HAS_DCACHE if SOC_ESP32P4_HPCORE
	select HAS_PM
	select HAS_POWEROFF
	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if SOC_ESP32P4_HPCORE

if SOC_SERIES_ESP32P4

menu "Cache config"

choice ESP32_CACHE_L2_SIZE_CHOICE
	prompt "L2 cache size"
	default ESP32_CACHE_L2_128KB
	help
	  L2 cache size to be set on application startup. The L2 cache is
	  carved out of HP SRAM, so a larger cache reduces usable SRAM.

config ESP32_CACHE_L2_128KB
	bool "128KB"

config ESP32_CACHE_L2_256KB
	bool "256KB"

config ESP32_CACHE_L2_512KB
	bool "512KB"

endchoice

config ESP32_CACHE_L2_SIZE
	hex
	default 0x20000 if ESP32_CACHE_L2_128KB
	default 0x40000 if ESP32_CACHE_L2_256KB
	default 0x80000 if ESP32_CACHE_L2_512KB

choice ESP32_CACHE_L2_LINE_SIZE_CHOICE
	prompt "L2 cache line size"
	default ESP32_CACHE_L2_LINE_64B if ESP32_CACHE_L2_128KB
	default ESP32_CACHE_L2_LINE_64B if ESP32_CACHE_L2_256KB
	default ESP32_CACHE_L2_LINE_128B if ESP32_CACHE_L2_512KB
	help
	  L2 cache line size to be set on application startup. 64B lines
	  are only valid for 128KB and 256KB cache sizes; the 512KB cache
	  is fixed to 128B lines.

config ESP32_CACHE_L2_LINE_64B
	bool "64 Bytes"
	depends on ESP32_CACHE_L2_128KB || ESP32_CACHE_L2_256KB

config ESP32_CACHE_L2_LINE_128B
	bool "128 Bytes"

endchoice

config ESP32_CACHE_L2_LINE_SIZE
	int
	default 64 if ESP32_CACHE_L2_LINE_64B
	default 128 if ESP32_CACHE_L2_LINE_128B

endmenu # Cache config

rsource "Kconfig.caps"

config ESP32P4_EMAC
	bool
	default y if ETH_ESP32
	default y if ETH_ESP32_DWC_ETHER_1000
	default y if MDIO_ESP32
	help
	  Hidden option to enable the ESP32-P4 Ethernet
	  MAC driver. Both Ethernet and MDIO depend on
	  this driver. This option allows enabling MDIO
	  independently of Ethernet.

config SOC_ESP32P4_REV_MIN_FULL
	int
	default 103 if SOC_ESP32P4_REV_1_3
	default 300 if SOC_ESP32P4_REV_3_0
	default 301 if SOC_ESP32P4_REV_3_1
	default 301
	help
	  Minimum supported ESP32-P4 chip revision in major * 100 + minor
	  format, matching what efuse_hal_chip_revision() returns at runtime.
	  Derived from the SOC_ESP32P4_REV_* symbol the board selects; defaults
	  to v3.1 (301), the floor of the v3.x family, when none is selected.

endif # SOC_SERIES_ESP32P4
