# Synopsys DesignWare MAC configuration options

# Copyright (c) 2021 BayLibre SAS
# SPDX-License-Identifier: Apache-2.0

menu "Synopsys DesignWare MAC driver"

DT_CHOSEN_Z_DTCM := zephyr,dtcm

config ETH_DWC_ETHER_QOS_CORE
	bool
	depends on NET_BUF_FIXED_DATA_SIZE
	select CACHE_MANAGEMENT if DCACHE
	help
	  This is a driver for the Synopsys DesignWare Ethernet MAC 10/100/1G Quality-of-Service,
	  also referred to as "dwc_ether_qos".
	  IP versions v4.x and v5.x are supported.

config ETH_DWC_ETHER_1000_CORE
	bool
	depends on NET_BUF_FIXED_DATA_SIZE
	select CACHE_MANAGEMENT if DCACHE
	help
	  This is a driver for the Synopsys DesignWare Ethernet MAC 10/100/1G Universal,
	  also referred to as "dwc_ether_mac10_100_1000_universal".
	  IP version v3.x is supported.

config ETH_ESP32_DWC_ETHER_1000
	bool "Driver for DWC Ethernet MAC-based ESP32"
	depends on !ETH_ESP32
	depends on SOC_SERIES_ESP32 || SOC_SERIES_ESP32P4
	depends on DT_HAS_ESPRESSIF_ESP32_ETH_ENABLED
	select ETH_DWC_ETHER_1000_CORE
	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
	default y
	help
	  This enables the Synopsys DesignWare MAC driver for ESP32 SoCs.

config ETH_STM32_DWC_ETHER_QOS
	bool "Driver for DWC Ethernet QoS-based STM32"
	depends on !ETH_STM32_HAL
	depends on SOC_SERIES_STM32H5X \
		   || SOC_SERIES_STM32H7X \
		   || SOC_SERIES_STM32H7RSX
	depends on DT_HAS_ST_STM32_ETHERNET_ENABLED
	select ETH_DWC_ETHER_QOS_CORE
	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
	select PINCTRL
	select HWINFO
	select CRC
	default y
	help
	  This enables the Synopsys DesignWare MAC driver on STM32 H5/H7/H7RS
	  series SoCs.

config ETH_STM32_DWC_ETHER_1000
	bool "Driver for DWC Ethernet MAC-based STM32"
	depends on !ETH_STM32_HAL
	depends on SOC_SERIES_STM32F7X || \
		   SOC_SERIES_STM32F4X || \
		   SOC_SERIES_STM32F2X || \
		   SOC_SERIES_STM32F1X
	depends on DT_HAS_ST_STM32_ETHERNET_ENABLED
	select ETH_DWC_ETHER_1000_CORE
	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT \
				 && !$(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
	select PINCTRL
	select HWINFO
	select CRC
	default y
	help
	  This enables the Synopsys DesignWare MAC driver for STM32 SoCs.
	  Applicable for STM32F1/F2/F4/F7 series; tested only on F2/F4/F7.

config ETH_DWMAC_MMU
	bool "Synopsys DesignWare MAC driver for MMU based platforms"
	depends on MMU
	depends on DT_HAS_SNPS_DESIGNWARE_ETHERNET_ENABLED
	select ETH_DWC_ETHER_QOS_CORE
	default y
	help
	  This enables the Synopsys DesignWare MAC driver on MMU based
	  platforms.

config ETH_DWC_ETHER_1000_CORE_EDFE
	bool
	depends on ETH_DWC_ETHER_1000_CORE
	depends on !SOC_SERIES_STM32F1X
	default y if PTP_CLOCK_DWC_MAC
	help
	  Increases the descriptor size to 32 bytes.

if ETH_DWC_ETHER_QOS_CORE || ETH_DWC_ETHER_1000_CORE

configdefault NET_BUF_ALIGNMENT
	default DCACHE_LINE_SIZE if DCACHE

config DWMAC_NB_TX_DESCS
	int "Number of entries in the transmit descriptor ring"
	default 16
	range 4 128
	help
	  A higher number allows for more packets to be queued which may
	  improve throughput, but that requires more transient memory.
	  However there must be enough descriptors to hold all fragments
	  of a full-size packet to be transmitted or the packet will be
	  dropped.

	  Fragment size is influenced by CONFIG_NET_BUF_DATA_SIZE.

config DWMAC_NB_RX_DESCS
	int "Number of entries in the receive descriptor ring"
	default 16
	range 4 128
	help
	  Received packets are spread across the required number of fragment
	  buffers. Each RX fragment has a size of CONFIG_NET_BUF_DATA_SIZE.
	  There is one descriptor entry per fragment.

	  A higher number allows for more packets to be received without
	  immediate intervention from the CPU but requires more transient
	  memory. A smaller number increases the risk of an overflow and
	  dropped packets.

config ETH_DWMAC_RX_REFILL_IRQ
	bool "Receive buffer refill in interrupt"
	default y
	help
	  Refill the receive buffer pool in the rx interrupt, if
	  possible, otherwise in the refill thread.

config ETH_DWMAC_RX_REFILL_THREAD_PRIORITY
	int "Receive buffer refill thread priority"
	default 0
	help
	  Priority level of the internal thread which is used to refill
	  the receive buffer pool.

config ETH_DWC_ETHER_TX_HW_CHECKSUM
	bool "Use TX hardware checksum"
	select NET_CHECKSUM_OFFLOAD_SUPPORTED if NET_L2_ETHERNET
	depends on !SOC_SERIES_ESP32P4
	default y
	help
	  Enable transmit checksum offload to enhance throughput
	  performances. Only supported when store and forward mode
	  is used for tx, which can't be used if the tx fifo is smaller
	  than the maximum frame size.

config ETH_DWC_ETHER_TX_HW_CHECKSUM_EN
	bool
	depends on ETH_DWC_ETHER_TX_HW_CHECKSUM
	depends on NET_CHECKSUM_OFFLOAD
	default y

config ETH_DWC_ETHER_RX_HW_CHECKSUM
	bool "Use RX hardware checksum"
	select NET_CHECKSUM_OFFLOAD_SUPPORTED if NET_L2_ETHERNET
	default y
	help
	  Enable receive checksum offload to enhance throughput
	  performances.

config ETH_DWC_ETHER_RX_HW_CHECKSUM_EN
	bool
	depends on ETH_DWC_ETHER_RX_HW_CHECKSUM
	depends on NET_CHECKSUM_OFFLOAD
	default y

rsource "Kconfig.ptp"

endif # ETH_DWC_ETHER_QOS_CORE || ETH_DWC_ETHER_1000_CORE

endmenu
