# ARM Cortex-A and Cortex-R platform configuration options

# Copyright (c) 2018 Marvell
# Copyright (c) 2018 Lexmark International, Inc.
# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
#
# SPDX-License-Identifier: Apache-2.0

# NOTE: We have the specific core implementations first and outside of the
# if CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R block so that SoCs can
# select which core they are using without having to select all the options
# related to that core. Everything else is captured inside the if
# CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not
# exposed if one selects a different ARM Cortex Family (Cortex-M).

config CPU_CORTEX_A7
	bool
	select CPU_AARCH32_CORTEX_A
	select ARMV7_A
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	help
	  This option signifies the use of a Cortex-A7 CPU.

config CPU_CORTEX_A9
	bool
	select CPU_AARCH32_CORTEX_A
	select ARMV7_A
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	help
	  This option signifies the use of a Cortex-A9 CPU.

config CPU_CORTEX_A32
	bool
	select CPU_AARCH32_CORTEX_A
	select AARCH32_ARMV8_A
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	help
	  This option signifies the use of a Cortex-A32 CPU.

if CPU_AARCH32_CORTEX_A

config ARMV7_A
	bool
	select ATOMIC_OPERATIONS_BUILTIN
	select ISA_ARM

# TODO: Introduce an ARM_A_PROFILE_AARCH32 capability flag selected by both
# ARMV7_A and AARCH32_ARMV8_A to simplify the conditional guards in shared code.
config AARCH32_ARMV8_A
	bool
	select ATOMIC_OPERATIONS_BUILTIN
	select ISA_ARM
	help
	  This option signifies the use of an ARMv8-A processor running in
	  the AArch32 execution state.

	  From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
	  The Armv8-A architecture targets the Applications profile and introduces
	  a 64-bit execution state (AArch64) alongside the 32-bit AArch32 state.
	  In AArch32 state, it provides a Virtual Memory System Architecture (VMSA)
	  based on a Memory Management Unit (MMU) and supports the A32 and T32
	  instruction sets.

	  UP only; SMP is not yet supported.

config AARCH32_ARMV8_A_MONITOR_INIT
	bool "Perform Monitor mode initialization at reset"
	depends on AARCH32_ARMV8_A
	help
	  Enable early Monitor mode (EL3 AArch32) initialization at reset,
	  analogous to the EL3 initialization performed in the arm64 port
	  (z_arm64_el3_init).

	  On ARMv8-A AArch32 platforms booting bare-metal without Trusted
	  Firmware-A, the core resets into Secure SVC mode. Certain system
	  registers are only accessible from Monitor mode, such as ICC_MSRE
	  (enables GICv3 CPU interface system register access). This option
	  briefly switches to Monitor mode at reset to configure such
	  registers before returning to SVC. This block executes on every
	  cpu at reset, before the SMP voting.

	  Enable when booting bare-metal in AArch32 Secure state with EL3
	  implemented in AArch32 (Monitor mode available).

	  Leave disabled when EL3 is AArch64-only, when Trusted Firmware-A
	  has already performed this initialization, or when booting in
	  Non-Secure state.

config ARMV7_A_NS
	bool "ARMv7-A Non-Secure state (Non-secure world of TrustZone)"
	depends on ARMV7_A
	help
	  Zephyr is running in ARM TrustZone Non-Secure state on an ARMv7-A core.

config ARMV7_EXCEPTION_STACK_SIZE
	int "Undefined Instruction and Abort stack size (in bytes)"
	default 256
	help
	  This option specifies the size of the stack used by the undefined
	  instruction and data abort exception handlers.

config ARMV7_FIQ_STACK_SIZE
	int "FIQ stack size (in bytes)"
	default 256
	help
	  This option specifies the size of the stack used by the FIQ handler.

config ARMV7_SVC_STACK_SIZE
	int "SVC stack size (in bytes)"
	default 512
	help
	  This option specifies the size of the stack used by the SVC handler.

config ARMV7_SYS_STACK_SIZE
	int "SYS stack size (in bytes)"
	default 1024
	help
	  This option specifies the size of the stack used by the system mode.

config RUNTIME_NMI
	default y

config GEN_ISR_TABLES
	default y

config GEN_IRQ_VECTOR_TABLE
	default n

config DCACHE_LINE_SIZE
	default 32

config ICACHE_LINE_SIZE
	default 32

endif # CPU_AARCH32_CORTEX_A

config CPU_CORTEX_R4
	bool
	select CPU_AARCH32_CORTEX_R
	select ARMV7_R
	select ARMV7_R_FP if CPU_HAS_FPU
	help
	  This option signifies the use of a Cortex-R4 CPU

config CPU_CORTEX_R5
	bool
	select CPU_AARCH32_CORTEX_R
	select ARMV7_R
	select ARMV7_R_FP if CPU_HAS_FPU
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	help
	  This option signifies the use of a Cortex-R5 CPU

config CPU_CORTEX_R7
	bool
	select CPU_AARCH32_CORTEX_R
	select ARMV7_R
	select ARMV7_R_FP if CPU_HAS_FPU
	help
	  This option signifies the use of a Cortex-R7 CPU

config CPU_CORTEX_R8
	bool
	select CPU_AARCH32_CORTEX_R
	select ARMV7_R
	select ARMV7_R_FP if CPU_HAS_FPU
	help
	  This option signifies the use of a Cortex-R8 CPU

config CPU_CORTEX_R52
	bool
	select CPU_AARCH32_CORTEX_R
	select AARCH32_ARMV8_R
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	select VFP_SP_D16 if !USE_SWITCH
	help
	  This option signifies the use of a Cortex-R52 CPU

config CPU_CORTEX_R52_CACHE_SEGREGATION
	bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
	depends on CPU_CORTEX_R52
	help
	  Control segregation of L1 I/D-Cache ways between Flash and AXIM.
	  Updates to the cache segregation controls are only permitted before the caches
	  have ever been enabled, following a system reset, otherwise the update is ignored.

config CPU_CORTEX_R52_ICACHE_FLASH_WAY
	int "L1 I-Cache Flash way"
	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
	range 0 4
	default 0
	help
	  Configure L1 I-Cache ways for Flash interface. Default is reset value, all
	  I-Cache ways are allocated for AXIM interface.

config CPU_CORTEX_R52_DCACHE_FLASH_WAY
	int "L1 D-Cache Flash way"
	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
	range 0 4
	default 0
	help
	  Configure L1 D-Cache ways for Flash interface. Default is reset value,
	  all D-Cache ways are allocated for AXIM interface.

if CPU_AARCH32_CORTEX_R

config ARMV7_R
	bool
	select ATOMIC_OPERATIONS_BUILTIN
	select ISA_ARM
	select ISA_THUMB2
	help
	  This option signifies the use of an ARMv7-R processor
	  implementation.

	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
	  The Armv7-R architecture implements a traditional Arm architecture with
	  multiple modes and supports a Protected Memory System Architecture
	  (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32)
	  and Thumb (T32) instruction sets.

config ARMV7_R_FP
	bool
	depends on ARMV7_R
	help
	  This option signifies the use of an ARMv7-R processor
	  implementation supporting the Floating-Point Extension.

config AARCH32_ARMV8_R
	bool
	select ATOMIC_OPERATIONS_BUILTIN
	select SCHED_IPI_SUPPORTED if SMP
	select ARCH_HAS_DIRECTED_IPIS
	help
	  This option signifies the use of an ARMv8-R AArch32 processor
	  implementation.

	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
	  The Armv8-R architecture targets at the Real-time profile. It introduces
	  virtualization at the highest security level while retaining the
	  Protected Memory System Architecture (PMSA) based on a Memory Protection
	  Unit (MPU). It supports the A32 and T32 instruction sets.

config ARMV7_EXCEPTION_STACK_SIZE
	int "Undefined Instruction and Abort stack size (in bytes)"
	default 256
	help
	  This option specifies the size of the stack used by the undefined
	  instruction and data abort exception handlers.

config ARMV7_FIQ_STACK_SIZE
	int "FIQ stack size (in bytes)"
	default 256
	help
	  This option specifies the size of the stack used by the FIQ handler.

config ARMV7_SVC_STACK_SIZE
	int "SVC stack size (in bytes)"
	default 512
	help
	  This option specifies the size of the stack used by the SVC handler.

config ARMV7_SYS_STACK_SIZE
	int "SYS stack size (in bytes)"
	default 1024
	help
	  This option specifies the size of the stack used by the system mode.

config RUNTIME_NMI
	default y

config GEN_ISR_TABLES
	default y

config GEN_IRQ_VECTOR_TABLE
	default n

config DISABLE_TCM_ECC
	bool "Disable ECC on TCM"
	help
	  This option disables ECC checks on Tightly Coupled Memory.

config DCACHE_LINE_SIZE
	default 64 if CPU_CORTEX_R52
	default 32

config ICACHE_LINE_SIZE
	default 64 if CPU_CORTEX_R52
	default 32

endif # CPU_AARCH32_CORTEX_R

config TEST_EXTRA_STACK_SIZE
	default 1024 if SMP
