In regards to "Can you clock SPI down to 24 Hz?":
 
CLK_SPI0 uses PBC clock domain (see below)
CLK_SPI1 uses PBA clock domain (see below)
page 663:
SPI baud rate clock is generated by dividing CLK_SPIx by n=1:255.  'n' is stored in the "SCBR" field (CSR0-8:15).  
Thus, if we want to run at 24 Hz, then maximum PBC or PBA frequency is 6.12 kHz.
That means one of the following subsystems is clocked at 6.12 kHz:
 
PBA clocks:
USART0
USART2
USART3
SPI1
I2S
TWI0:1
PWM
D2A0:1
AComparators
TC1
QD0:1
async timer
freqmeter
 
PBC clocks:
USART1
USART4
A2D0:1
SPI0
TC0
TWI2
 
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I can't live with that.  I'll hope I don't have too many interrupts and just bit bang it.  
 
...
 
However, to finish the exercise:
Can we generate a 6.12 kHz PBC clock when the CPU clock is, for example, 16 MHz?
 
Page 52:
f(PBx)=f(main)/2^(PBSEL+1)
 
Page 63:
PBSEL is only 3 bits, so PBSEL(max)= 111b=8d
 
Thus, if our main clock is 16 MHz, then the slowest we can run PBC is:
f(PBC)=16 MHz/2^8= 62.5 kHz
 
Since CLK_SPI0 is derived from PBC, and can be divided by 255, that means CLK_SPI0 would run at 245 Hz.
Thus, the minimum SPI baud rate with a 16 MHz oscillator is 245 Hz.  
 
...
 
If we wanted to clock SPI@ 24 Hz, then the fastest system oscillator we could use is:
 
6.12 kHz = f(main)/2^8
Thus, f(main)=1.566 MHz
 
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tl;dr: Can't clock SPI@24 Hz unless system oscillator is 1.566 MHz or less.