pkgbase = yosys-git
	pkgdesc = A framework for RTL synthesis
	pkgver = 0.67.r40.g45ea2b8
	pkgrel = 1
	url = https://github.com/YosysHQ/yosys
	arch = x86_64
	arch = i686
	arch = aarch64
	license = ISC
	checkdepends = iverilog
	makedepends = cmake
	makedepends = git
	makedepends = ninja
	makedepends = pybind11
	makedepends = python-build
	makedepends = python-cxxheaderparser
	makedepends = python-installer
	makedepends = python-setuptools
	makedepends = python-wheel
	depends = gtkwave
	depends = tcl
	depends = python
	depends = python-click
	optdepends = graphviz: Schematics display support
	optdepends = xdot: Design netlist display support
	provides = yosys
	conflicts = yosys
	options = !lto
	source = yosys::git+https://github.com/YosysHQ/yosys.git
	source = 0001-verilog-port-renaming.patch
	source = 0002-verilog-port-renaming-tests.patch
	sha256sums = SKIP
	sha256sums = ac658080f906a24d9015e35276ea58ee3565cf8d4171da9bd11f1e973fec5bda
	sha256sums = 11913a84a3d51e5a71d194a8e0ae5092672d083d79bf55c42b2d5d0e4ac6d6d7

pkgname = yosys-git
