declare hidden i1 @__zluda_ptx_impl_vote_sync_all_pred(i1, i32) #0

declare hidden i32 @__zluda_ptx_impl_sreg_tid(i8) #0

declare hidden i32 @__zluda_ptx_impl_sreg_laneid() #0

define amdgpu_kernel void @vote_all_sub(ptr addrspace(4) byref(i64) %"57") #1 {
  %"58" = alloca i32, align 4, addrspace(5)
  %"59" = alloca i32, align 4, addrspace(5)
  %"60" = alloca i1, align 1, addrspace(5)
  %"61" = alloca i1, align 1, addrspace(5)
  %"62" = alloca i32, align 4, addrspace(5)
  %"63" = alloca i64, align 8, addrspace(5)
  %"74" = alloca i64, align 8, addrspace(5)
  br label %1

1:                                                ; preds = %0
  br label %"54"

"54":                                             ; preds = %1
  %2 = load i64, ptr addrspace(4) %"57", align 8
  store i64 %2, ptr addrspace(5) %"63", align 8
  %"44" = call i32 @__zluda_ptx_impl_sreg_laneid()
  store i32 %"44", ptr addrspace(5) %"58", align 4
  %"46" = call i32 @__zluda_ptx_impl_sreg_tid(i8 0)
  store i32 %"46", ptr addrspace(5) %"59", align 4
  %3 = load i32, ptr addrspace(5) %"58", align 4
  %4 = icmp eq i32 %3, 0
  store i1 %4, ptr addrspace(5) %"60", align 1
  store i1 false, ptr addrspace(5) %"61", align 1
  %5 = load i1, ptr addrspace(5) %"60", align 1
  br i1 %5, label %"12", label %"21"

"21":                                             ; preds = %"54"
  %"71" = call i1 @__zluda_ptx_impl_vote_sync_all_pred(i1 true, i32 -1)
  store i1 %"71", ptr addrspace(5) %"61", align 1
  br label %"12"

"12":                                             ; preds = %"21", %"54"
  %6 = load i1, ptr addrspace(5) %"61", align 1
  %"72" = select i1 %6, i32 1, i32 0
  store i32 %"72", ptr addrspace(5) %"62", align 4
  %7 = load i32, ptr addrspace(5) %"59", align 4
  %8 = zext i32 %7 to i64
  %"75" = mul i64 %8, 4
  store i64 %"75", ptr addrspace(5) %"74", align 8
  %9 = load i64, ptr addrspace(5) %"63", align 8
  %10 = load i64, ptr addrspace(5) %"74", align 8
  %"77" = add i64 %9, %10
  store i64 %"77", ptr addrspace(5) %"63", align 8
  %11 = load i64, ptr addrspace(5) %"63", align 8
  %12 = load i32, ptr addrspace(5) %"62", align 4
  %"82" = inttoptr i64 %11 to ptr
  store i32 %12, ptr %"82", align 4
  ret void
}

attributes #0 = { "amdgpu-ieee"="false" "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="dynamic" "denormal-fp-math-f32"="dynamic" "no-trapping-math"="true" "target-features"="+wavefrontsize32,-wavefrontsize64,+cumode,+precise-memory" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-ieee"="false" "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "target-features"="+wavefrontsize32,-wavefrontsize64,+cumode,+precise-memory" "uniform-work-group-size"="true" }
