Spike, the RISC-V ISA Simulator, implements a functional model of one or more
RISC-V harts. It is named after the golden spike used to celebrate the
completion of the US transcontinental railway.

Spike supports the following RISC-V ISA features:

    RV32I and RV64I base ISAs, v2.1
    Zifencei extension, v2.0
    Zicsr extension, v2.0
    M extension, v2.0
    A extension, v2.1
    F extension, v2.2
    D extension, v2.2
    Q extension, v2.2
    C extension, v2.0
    V extension, v0.8-draft-20191118, w/ Zvlsseg, w/o Zvamo/Zvediv, (requires a
                 64-bit host)
    Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
    Machine, Supervisor, and User modes, v1.11
    Debug v0.14

