// Module included in the following assemblies:
//
// * scalability_and_performance/ztp_far_edge/ztp-vdu-validating-cluster-tuning.adoc

:_mod-docs-content-type: REFERENCE
[id="ztp-du-firmware-config-reference_{context}"]
= Recommended firmware configuration for vDU cluster hosts

[role="_abstract"]
Use the following table as the basis to configure the cluster host firmware for vDU applications running on {product-title} {product-version}.

[NOTE]
====
The following table is a general recommendation for vDU cluster host firmware configuration. Exact firmware settings will depend on your requirements and specific hardware platform. Automatic setting of firmware is not handled by the zero touch provisioning pipeline.
====

.Recommended cluster host firmware settings
[cols="1,1,3", options="header"]
|====
|Firmware setting
|Configuration
|Description

|HyperTransport (HT)
|Enabled
|HyperTransport (HT) bus is a bus technology developed by AMD. HT provides a high-speed link between the components in the host memory and other system peripherals.

|UEFI
|Enabled
|Enable booting from UEFI for the vDU host.

|CPU Power and Performance Policy
|Performance
|Set CPU Power and Performance Policy to optimize the system for performance over energy efficiency.

|Uncore Frequency Scaling
|Disabled
|Disable Uncore Frequency Scaling to prevent the voltage and frequency of non-core parts of the CPU from being set independently.

|Uncore Frequency
|Maximum
|Sets the non-core parts of the CPU such as cache and memory controller to their maximum possible frequency of operation.

|Performance P-limit
|Disabled
|Disable Performance P-limit to prevent the Uncore frequency coordination of processors.

|Enhanced Intel(R) SpeedStep Tech
|Enabled
|Enable Enhanced Intel SpeedStep to allow the system to dynamically adjust processor voltage and core frequency that decreases power consumption and heat production in the host.

|Intel(R) Turbo Boost Technology
|Enabled
|Enable Turbo Boost Technology for Intel-based CPUs to automatically allow processor cores to run faster than the rated operating frequency if they are operating below power, current, and temperature specification limits.

|Intel Configurable TDP
|Enabled
|Enables Thermal Design Power (TDP) for the CPU.

|Configurable TDP Level
|Level 2
|TDP level sets the CPU power consumption required for a particular performance rating. TDP level 2 sets the CPU to the most stable performance level at the cost of power consumption.

|Energy Efficient Turbo
|Disabled
|Disable Energy Efficient Turbo to prevent the processor from using an energy-efficiency based policy.

|Hardware P-States
|Enabled or Disabled
|Enable OS-controlled P-States to allow power saving configurations. Disable `P-states` (performance states) to optimize the operating system and CPU for performance over power consumption.

|Package C-State
|C0/C1 state
|Use C0 or C1 states to set the processor to a fully active state (C0) or to stop CPU internal clocks running in software (C1).

|C1E
|Disabled
|CPU Enhanced Halt (C1E) is a power saving feature in Intel chips. Disabling C1E prevents the operating system from sending a halt command to the CPU when inactive.

|Processor C6
|Disabled
|C6 power-saving is a CPU feature that automatically disables idle CPU cores and cache. Disabling C6 improves system performance.

|Sub-NUMA Clustering
|Disabled
|Sub-NUMA clustering divides the processor cores, cache, and memory into multiple NUMA domains. Disabling this option can increase performance for latency-sensitive workloads.
|====

[NOTE]
====
Enable global SR-IOV and VT-d settings in the firmware for the host. These settings are relevant to bare-metal environments.
====

[NOTE]
====
Enable both `C-states` and OS-controlled `P-States` to allow per pod power management.
====
