
#ifndef __SKX_PERFEVTSEL_WRITE_MASKS_H__
#define __SKX_PERFEVTSEL_WRITE_MASKS_H__

// Various masks for PerfEvtSel registers
// Should be used to directly program the aforementioned
// register by means of msr-tools program.

#define MEM_LOAD_RETIRED_L1_HIT       0x004301d1
#define MEM_LOAD_RETIRED_L2_HIT       0x004302d1
#define MEM_LOAD_RETIRED_L3_HIT       0x004304d1
#define MEM_LOAD_RETIRED_L1_MISS      0x004308d1
#define MEM_LOAD_RETIRED_L2_MISS      0x004310d1
#define MEM_LOAD_RETIRED_L3_MISS      0x004320d1
#define MEM_LOAD_RETIRED_FB_HIT       0x004340d1
#define MEM_LOAD_RETIRED_ALL_LOADS    0x004381d0
#define L2_RQSTS_MISS                 0x00433f24
#define L1D_REPLACEMENTS              0x00430151
#define L2_LINES_IN                   0x00431ff1
#define IDI_MISC_WB_DOWNGRADE         0x004304fe
#define FREQ_MAX_LIMIT_THERMAL_CYCLES 0x00400004
#define FREQ_MAX_LIMIT_POWER_CYCLES   0x00400005
#define MCP_PROCHOT_CYCLES            0x00400006
#define FREQ_TRANS_CYCLES             0x00400074
#define FREQ_MAX_LIMIT_THERMAL_CYCLES 0x00400004
#define XSNP_RESP_EVICT_RSP_HITFSE    0x00408132
#define SF_EVICTION_M_STATE           0x0040013d
#define SF_EVICTION_E_STATE           0x0040023d
#define SF_EVICTION_S_STATE           0x0040043d
#define CPU_CLK_UNHALTED_KERNEL       0x0042003c
#define CPU_CLK_UNHALTED_REF_XCLK     0x0063013c
#define INSTR_RETIRED_KERNEL          0x004200c0
#define OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_READ_UK 0x004310b0
#define OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_READ_U  0x004110b0
#define OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_READ_K  0x004210b0
#define INSTR_RETIRED_ANY_UK          0x00430100
#define INSTR_RETIRED_ANY_K           0x00420100
#define INSTR_RETIRED_ANY_U           0x00410100
#define CPU_CLK_UNHALTED_THREAD_UK    0x00430200
#define CPU_CLK_UNHALTED_THREAD_K     0x00420200
#define CPU_CLK_UNHALTED_THREAD_U     0x00410200
#define CPU_CLK_UNHALTED_REF_TSC_UK   0x00430300
#define CPU_CLK_UNHALTED_REF_TSC_K    0x00420300
#define CPU_CLK_UNHALTED_REF_TSC_U    0x00410300
#define LD_BLOCKS_STORE_FORWARD_UK    0x00430203
#define LD_BLOCKS_STORE_FORWARD_K     0x00410203
#define LD_BLOCKS_STORE_FORWARD_U     0x00420203
#define LD_BLOCKS_NO_SR_UK            0x00430803
#define LD_BLOCKS_NO_SR_K             0x00420803
#define LD_BLOCKS_NO_SR_U             0x00410803
#define LD_BLOCKS_PARTIAL_ADDRESS_ALIAS_UK 0x00430107
#define LD_BLOCKS_PARTIAL_ADDRESS_ALIAS_K  0x00420107
#define LD_BLOCKS_PARTIAL_ADDRESS_ALIAS_U  0x00410107
#define DTLB_LOAD_MISSES_MISS_CAUSES_A_WALK_UK 0x00430108
#define DTLB_LOAD_MISSES_MISS_CAUSES_A_WALK_K  0x00420108
#define DTLB_LOAD_MISSES_MISS_CAUSES_A_WALK_U  0x00410108
#define DTLB_LOAD_MISSES_WALK_COMPLETED_4K_UK  0x00430208
#define DTLB_LOAD_MISSES_WALK_COMPLETED_4K_K   0x00420208
#define DTLB_LOAD_MISSES_WALK_COMPLETED_4K_U   0x00410208
#define DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M_UK  0x00430408
#define DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M_K   0x00420408
#define DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M_U   0x00410408
#define DTLB_LOAD_MISSES_WALK_COMPLETED_1G_UK     0x00430808
#define DTLB_LOAD_MISSES_WALK_COMPLETED_1G_K      0x00420808
#define DTLB_LOAD_MISSES_WALK_COMPLETED_1G_U      0x00410808
#define DTLB_LOAD_MISSES_WALK_COMPLETED_UK        0x00430e08
#define DTLB_LOAD_MISSES_WALK_COMPLETED_K         0x00420e08
#define DTLB_LOAD_MISSES_WALK_COMPLETED_U         0x00410e08
#define DTLB_LOAD_MISSES_WALK_PENDING_UK          0x00431008
#define DTLB_LOAD_MISSES_WALK_PENDING_K           0x00421008
#define DTLB_LOAD_MISSES_WALK_PENDING_U           0x00411008
#define DTLB_LOAD_MISSES_WALK_ACTIVE_UK           0x01431008
#define DTLB_LOAD_MISSES_WALK_ACTIVE_K            0x01421008
#define DTLB_LOAD_MISSES_WALK_ACTIVE_U            0x01411008
#define DTLB_LOAD_MISSES_STLB_HIT_UK              0x00432028
#define DTLB_LOAD_MISSES_STLB_HIT_K               0x00422028
#define DTLB_LOAD_MISSES_STLB_HIT_U               0x00412028
#define INT_MISC_RECOVERY_CYCLES_UK               0x0043010D
#define INT_MISC_RECOVERY_CYCLES_K                0x0042010D
#define INT_MISC_RECOVERY_CYCLES_U                0x0041010D
#define INT_MISC_RECOVERY_CYCLES_ANY_SET_UK       0x0063010D
#define INT_MISC_RECOVERY_CYCLES_ANY_SET_K        0x0062010D
#define INT_MISC_RECOVERY_CYCLES_ANY_SET_U        0x0061010D
#define INT_MISC_CLEAR_RESTEER_CYCLES_UK          0x0043800D
#define INT_MISC_CLEAR_RESTEER_CYCLES_K           0x0042800D
#define INT_MISC_CLEAR_RESTEER_CYCLES_U           0x0041800D
#define UOPS_ISSUED_STALL_CYCLES_UK               0x0043010e
#define UOPS_ISSUED_STALL_CYCLES_K                0x0042010e
#define UOPS_ISSUED_STALL_CYCLES_U                0x0041010e
#define UOPS_ISSUED_ANY_UK                        0x0043010e
#define UOPS_ISSUED_ANY_K                         0x0042010e
#define UOPS_ISSUED_ANY_U                         0x0041010e
#define UOPS_ISSUED_VECTOR_WIDTH_MISMATCH_UK      0x0043020e
#define UOPS_ISSUED_VECTOR_WIDTH_MISMATCH_K       0x0042020e
#define UOPS_ISSUED_VECTOR_WIDTH_MISMATCH_U       0x0041020e 
#define UOPS_ISSUED_SLOW_LEA_UK                   0x0043200e
#define UOPS_ISSUED_SLOW_LEA_K                    0x0042200e
#define UOPS_ISSUED_SLOW_LEA_U                    0x0041200e
#define ARITH_DIVIDER_ACTIVE_UK_CMASK             0x01430114
#define ARITH_DIVIDER_ACTIVE_K_CMASK              0x01420114
#define ARITH_DIVIDER_ACTIVE_U_CMASK              0x01410114  
#define L2_RQSTS_DEMAND_DATA_RD_MISS_UK           0x00432124
#define L2_RQSTS_DEMAND_DATA_RD_MISS_K            0x00422124
#define L2_RQSTS_DEMAND_DATA_RD_MISS_U            0x00412124
#define L2_RQSTS_RFO_MISS_UK                      0x00432224
#define L2_RQSTS_RFO_MISS_K                       0x00422224
#define L2_RQSTS_RFO_MISS_U                       0x00412224
#define L2_RQSTS_CODE_RD_MISS_UK                  0x00432424
#define L2_RQSTS_CODE_RD_MISS_K                   0x00422424
#define L2_RQSTS_CODE_RD_MISS_U                   0x00412424
#define L2_RQSTS_ALL_DEMAND_MISS_UK               0x00432724
#define L2_RQSTS_ALL_DEMAND_MISS_K                0x00422724
#define L2_RQSTS_ALL_DEMAND_MISS_U                0x00412724
#define L2_RQSTS_PF_MISS_UK                       0x00433824
#define L2_RQSTS_PF_MISS_K                        0x00423824
#define L2_RQSTS_PF_MISS_U                        0x00413824
#define L2_RQSTS_MISS_UK                          0x00433f24
#define L2_RQSTS_MISS_K                           0x00423f24
#define L2_RQSTS_MISS_U                           0x00413f24 
#define L2_RQSTS_DEMAND_DATA_RD_HIT_UK            0x0043c124
#define L2_RQSTS_DEMAND_DATA_RD_HIT_K             0x0042c124
#define L2_RQSTS_DEMAND_DATA_RD_HIT_U             0x0041c124
#define L2_RQSTS_RFO_HIT_UK                       0x0043c224
#define L2_RQSTS_RFO_HIT_K                        0x0042c224
#define L2_RQSTS_RFO_HIT_U                        0x0041c224
#define L2_RQSTS_CODE_RD_HIT_UK                   0x0043c424
#define L2_RQSTS_CODE_RD_HIT_K                    0x0042c424
#define L2_RQSTS_CODE_RD_HIT_U                    0x0041c424
#define L2_RQSTS_PF_HIT_UK                        0x0043d124
#define L2_RQSTS_PF_HIT_K                         0x0042d124
#define L2_RQSTS_PF_HIT_U                         0x0041d124
#define L2_RQSTS_ALL_DEMAND_DATA_RD_UK            0x0043e124
#define L2_RQSTS_ALL_DEMAND_DATA_RD_K             0x0042e124
#define L2_RQSTS_ALL_DEMAND_DATA_RD_U             0x0041e124
#define L2_RQSTS_ALL_RFO_UK                       0x0043e224
#define L2_RQSTS_ALL_RFO_K                        0x0042e224
#define L2_RQSTS_ALL_RFO_U                        0x0041e224
#define L2_RQSTS_ALL_CODE_RD_UK                   0x0043e424
#define L2_RQSTS_ALL_CODE_RD_K                    0x0042e424
#define L2_RQSTS_ALL_CODE_RD_U                    0x0041e424
#define L2_RQSTS_ALL_DEMAND_REFERENCES_UK         0x0043e724
#define L2_RQSTS_ALL_DEMAND_REFERENCES_K          0x0042e724
#define L2_RQSTS_ALL_DEMAND_REFERENCES_U          0x0041e724
#define L2_RQSTS_ALL_PF_UK                        0x0043e824
#define L2_RQSTS_ALL_PF_K                         0x0042e824
#define L2_RQSTS_ALL_PF_U                         0x0041e824
#define L2_RQSTS_REFERENCES_UK                    0x0043ff24
#define L2_RQSTS_REFERENCES_K                     0x0042ff24
#define L2_RQSTS_REFERENCES_U                     0x0041ff24
#define CORE_POWER_LVL0_TURBO_LICENSE_UK          0x00430728
#define CORE_POWER_LVL0_TURBO_LICENSE_K           0x00420728
#define CORE_POWER_LVL0_TURBO_LICENSE_U           0x00410728
#define CORE_POWER_LVL1_TURBO_LICENSE_UK          0x00431828
#define CORE_POWER_LVL1_TURBO_LICENSE_K           0x00421828
#define CORE_POWER_LVL1_TURBO_LICENSE_U           0x00411828
#define CORE_POWER_LVL2_TURBO_LICENSE_UK          0x00432028
#define CORE_POWER_LVL2_TURBO_LICENSE_K           0x00422028
#define CORE_POWER_LVL2_TURBO_LICENSE_U           0x00412028
#define CORE_POWER_THROTTLE_UK                    0x00434028
#define CORE_POWER_THROTTLE_K                     0x00424028
#define CORE_POWER_THROTTLE_U                     0x00414028
#define LONGEST_LAT_CACHE_MISS_UK                 0x0043412e
#define LONGEST_LAT_CACHE_MISS_K                  0x0042412e
#define LONGEST_LAT_CACHE_MISS_U                  0x0041412e
#define LONGEST_LAT_CACHE_REFERENCE_UK            0x00434f2e
#define LONGEST_LAT_CACHE_REFERENCE_K             0x00424f2e
#define LONGEST_LAT_CACHE_REFERENCE_U             0x00414f2e
#define SW_PREFETCH_ACCESS_NTA_UK                 0x00430132
#define SW_PREFETCH_ACCESS_NTA_K                  0x00420132
#define SW_PREFETCH_ACCESS_NTA_U                  0x00410132
#define SW_PREFETCH_ACCESS_T0_UK                  0x00430232
#define SW_PREFETCH_ACCESS_T0_K                   0x00420232
#define SW_PREFETCH_ACCESS_T0_U                   0x00410232
#define SW_PREFETCH_ACCESS_T1_T2_UK               0x00430432
#define SW_PREFETCH_ACCESS_T1_T2_K                0x00420432
#define SW_PREFETCH_ACCESS_T1_T2_U                0x00410432
#define SW_PREFETCH_ACCESS_PREFETCHW_UK           0x00430832
#define SW_PREFETCH_ACCESS_PREFETCHW_K            0x00420832
#define SW_PREFETCH_ACCESS_PREFETCHW_U            0x00410832
#define CPU_CLK_UNHALTED_THREAD_P_UK              0x0043003c
#define CPU_CLK_UNHALTED_THREAD_P_K               0x0042003c
#define CPU_CLK_UNHALTED_THREAD_P_U               0x0041003C
#define CPU_CLK_UNHALTED_THREAD_P_ANY_UK          0x0063003c
#define CPU_CLK_UNHALTED_THREAD_P_ANY_K           0x0062003c
#define CPU_CLK_UNHALTED_THREAD_P_ANY_U           0x0061003c
#define CPU_CLK_UNHALTED_RING0_TRANS_CM_ED_UK     0x0147003c
#define CPU_CLK_UNHALTED_RING0_TRANS_CM_ED_K      0x0146003c
#define CPU_CLK_UNHALTED_RING0_TRANS_CM_ED_U      0x0145003c
#define CPU_CLK_THREAD_UNHALTED_REF_XCLK_UK       0x0043013c
#define CPU_CLK_THREAD_UNHALTED_REF_XCLK_K        0x0042013c
#define CPU_CLK_THREAD_UNHALTED_REF_XCLK_U        0x0041013c
#define CPU_CLK_THREAD_UNHALTED_REF_XCLK_ANY_UK   0x0063013c
#define CPU_CLK_THREAD_UNHALTED_REF_XCLK_ANY_K    0x0062013c
#define CPU_CLK_THREAD_UNHALTED_REF_XCLK_ANY_U    0x0061013c
#define CPU_CLK_UNHALTED_REF_XCLK_ANY_UK          0x0063013c
#define CPU_CLK_UNHALTED_REF_XCLK_ANY_K           0x0062013c
#define CPU_CLK_UNHALTED_REF_XCLK_ANY_U           0x0061013c
#define CPU_CLK_UNHALTED_REF_XCLK_UK              0x0043013c
#define CPU_CLK_UNHALTED_REF_XCLK_K               0x0042013c
#define CPU_CLK_UNHALTED_REF_XCLK_U               0x0041013c
#define CPU_CLK_THREAD_UNHALTED_ONE_THREAD_ACTIVE_UK 0x0043023c
#define CPU_CLK_THREAD_UNHALTED_ONE_THREAD_ACTIVE_K  0x0042023c
#define CPU_CLK_THREAD_UNHALTED_ONE_THREAD_ACTIVE_U  0x0041023c
#define CPU_CLK_UNHALTED_ONE_THREAD_ACTIVE_UK        0x0043023c
#define CPU_CLK_UNHALTED_ONE_THREAD_ACTIVE_K         0x0042023c
#define CPU_CLK_UNHALTED_ONE_THREAD_ACTIVE_U         0x0041023c
#define L1D_PEND_MISS_PENDING_CYCLES_CM_UK           0x01430148
#define L1D_PEND_MISS_PENDING_CYCLES_CM_K            0x01420148
#define L1D_PEND_MISS_PENDING_CYCLES_CM_U            0x01410148
#define L1D_PEND_MISS_PENDING_UK                     0x00430148
#define L1D_PEND_MISS_PENDING_K                      0x00420148
#define L1D_PEND_MISS_PENDING_U                      0x00410148
#define L1D_PEND_MISS_PENDING_CYCLES_ANY_CM_UK       0x01630148
#define L1D_PEND_MISS_PENDING_CYCLES_ANY_CM_K        0x01620148
#define L1D_PEND_MISS_FB_FULL_UK                     0x00430248
#define L1D_PEND_MISS_FB_FULL_K                      0x00420248
#define L1D_PEND_MISS_FB_FULL_U                      0x00410248
#define DTLB_STORE_MISSES_CAUSES_A_WALK_UK           0x00430149
#define DTLB_STORE_MISSES_CAUSES_A_WALK_K            0x00420149
#define DTLB_STORE_MISSES_CAUSES_A_WALK_U            0x00410149
#define DTLB_STORE_MISSES_WALK_COMPLETED_4K_UK       0x00430249
#define DTLB_STORE_MISSES_WALK_COMPLETED_4K_K        0x00420249
#define DTLB_STORE_MISSES_WALK_COMPLETED_4K_U        0x00410249
#define DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M_UK    0x00430449
#define DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M_K     0x00420449
#define DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M_U     0x00410449
#define DTLB_STORE_MISSES_WALK_COMPLETED_1G_UK       0x00430849
#define DTLB_STORE_MISSES_WALK_COMPLETED_1G_K        0x00420849
#define DTLB_STORE_MISSES_WALK_COMPLETED_1G_U        0x00410849
#define DTLB_STORE_MISSES_WALK_COMPLETED_UK          0x00430e49
#define DTLB_STORE_MISSES_WALK_COMPLETED_K           0x00420e49
#define DTLB_STORE_MISSES_WALK_COMPLETED_U           0x00410e49
#define DTLB_STORE_MISSES_WALK_PENDING_UK            0x00431049
#define DTLB_STORE_MISSES_WALK_PENDING_K             0x00421049
#define DTLB_STORE_MISSES_WALK_PENDING_U             0x00411049
#define DTLB_STORE_MISSES_WALK_ACTIVE_CM_UK          0x01431049
#define DTLB_STORE_MISSES_WALK_ACTIVE_CM_K           0x01421049
#define DTLB_STORE_MISSES_WALK_ACTIVE_CM_U           0x01411049
#define DTLB_STORE_MISSES_STLB_HIT_UK                0x00432049
#define DTLB_STORE_MISSES_STLB_HIT_K                 0x00422049
#define DTLB_STORE_MISSES_STLB_HIT_U                 0x00412049
#define LOAD_HIT_PRE_SW_PF_UK                        0x0043014c
#define LOAD_HIT_PRE_SW_PF_K                         0x0042014c
#define LOAD_HIT_PRE_SW_PF_U                         0x0041014c
#define EPT_WALK_PENDING_UK                          0x0043104f
#define EPT_WALK_PENDING_K                           0x0042104f
#define EPT_WALK_PENDING_U                           0x0041104f
#define L1D_REPLACEMENT_UK                           0x00430151
#define L1D_REPLACEMENT_K                            0x00420151
#define L1D_REPLACEMENT_U                            0x00410151
#define TX_MEM_ABORT_CONFLICT_UK                     0x00430154
#define TX_MEM_ABORT_CONFLICT_K                      0x00420145
#define TX_MEM_ABORT_CONFLICT_U                      0x00410145
#define TX_MEM_ABORT_CAPACITY_UK                     0x00430254
#define TX_MEM_ABORT_CAPACITY_K                      0x00420254
#define TX_MEM_ABORT_CAPACITY_U                      0x00410254
#define TX_MEM_ABORT_HLE_STORE_TO_ELIDED_LOCK_UK     0x00430454
#define TX_MEM_ABORT_HLE_STORE_TO_ELIDED_LOCK_K      0x00420454
#define TX_MEM_ABORT_HLE_STORE_TO_ELIDED_LOCK_U      0x00410454
#define TX_MEM_ABORT_HLE_ELISION_BUFFER_NOT_EMPTY_UK 0x00430854
#define TX_MEM_ABORT_HLE_ELISION_BUFFER_NOT_EMPTY_K  0x00420854
#define TX_MEM_ABORT_HLE_ELISION_BUFFER_NOT_EMPTY_U  0x00410854
#define TX_MEM_ABORT_HLE_ELISION_BUFFER_MISMATCH_UK  0x00431054
#define TX_MEM_ABORT_HLE_ELISION_BUFFER_MISMATCH_K   0x00421054
#define TX_MEM_ABORT_HLE_ELISION_BUFFER_MISMATCH_U   0x00411054
#define PARTIAL_RAT_STALLS_SCOREBOARD_UK             0x00430159
#define PARTIAL_RAT_STALLS_SCOREBOARD_K              0x00420159
#define PARTIAL_RAT_STALLS_SCOREBOARD_U              0x00410159
#define RS_EVENT_EMPTY_END_UK                        0x01c7015e 
#define RS_EVENT_EMPTY_END_K                         0x01c6015e
#define RS_EVENT_EMPTY_END_U                         0x01c5015e
#define RS_EVENTS_EMPTY_CYCLES_UK                    0x0043015e
#define RS_EVENTS_EMPTY_CYCLES_K                     0x0042015e
#define RS_EVENTS_EMPTY_CYCLES_U                     0x0041015e
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_UK 0x01430160
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_K  0x01420160
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_U  0x01410160
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_UK 0x00430160
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_K  0x00420160
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_U  0x00410160
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_GE_6_UK 0x06430160
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_GE_6_K 0x06420160
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_GE_6_U 0x06410160
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD_UK  0x00430260
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD_K   0x00420260
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD_U   0x00410260
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD_UK 0x01430260
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD_K  0x01420260
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD_U  0x01410260
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO_UK  0x00430460
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO_K   0x00420460
#define OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO_U   0x00410460
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO_UK 0x01430460
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO_K 0x01420460
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO_U 0x01410460
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD_UK 0x01430860
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD_K  0x01420860
#define OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD_U  0x01410860
#define OFFCORE_REQUESTS_OUTSTANDING_ALL_DATA_RD_UK 0x00430860
#define OFFCORE_REQUESTS_OUTSTANDING_ALL_DATA_RD_K  0x00420860
#define OFFCORE_REQUESTS_OUTSTANDING_ALL_DATA_RD_U  0x00410860
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_UK 0x00431060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_K 0x00421060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_U 0x00411060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_GE_6_UK 0x06431060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_GE_6_K  0x06421060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_GE_6_U  0x06411060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_UK 0x01431060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_K  0x01421060
#define OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_U  0x01411060
#define IDQ_MITE_CYCLES_UK 0x01430479
#define IDQ_MITE_CYCLES_K  0x01420479
#define IDQ_MITE_CYCLES_U  0x01410479
#define IDQ_MITE_UOPS_UK   0x00430479
#define IDQ_MITE_UOPS_K    0x00420479
#define IDQ_MITE_UOPS_U    0x00410479
#define IDQ_DSB_CYCLES_UK  0x01430879
#define IDQ_DSB_CYCLES_K   0x01420879
#define IDQ_DSB_CYCLES_U   0x01410879
#define IDQ_DSB_UOPS_UK    0x00430879
#define IDQ_DSB_UOPS_K     0x00420879
#define IDQ_DSB_UOPS_U     0x00410879
#define IDQ_MS_DSB_CYCLES_UK 0x01431079
#define IDQ_MS_DSB_CYCLES_K  0x01421079
#define IDQ_MS_DSB_CYCLES_U  0x01411079
#define IDQ_ALL_DSB_CYCLES_ANY_UOPS_UK 0x01431879
#define IDQ_ALL_DSB_CYCLES_ANY_UOPS_K  0x01421879
#define IDQ_ALL_DSB_CYCLES_ANY_UOPS_U  0x01411879
#define IDQ_ALL_DSB_CYCLES_4_UOPS_UK   0x04431879
#define IDQ_ALL_DSB_CYCLES_4_UOPS_K    0x04421879
#define IDQ_ALL_DSB_CYCLES_4_UOPS_U    0x04411879
#define IDQ_MS_MITE_UOPS_UK 0x00432079
#define IDQ_MS_MITE_UOPS_K  0x00422079
#define IDQ_MS_MITE_UOPS_U  0x00412079
#define IDQ_ALL_MITE_CYCLES_ANY_UOPS_UK 0x01432479
#define IDQ_ALL_MITE_CYCLES_ANY_UOPS_K  0x01422479
#define IDQ_ALL_MITE_CYCLES_ANY_UOPS_U  0x01412479
#define IDQ_ALL_MITE_CYCLES_4_UOPS_UK   0x04432479
#define IDQ_ALL_MITE_CYCLES_4_UOPS_K    0x04422479
#define IDQ_ALL_MITE_CYCLES_4_UOPS_U    0x04412479
#define IDQ_MS_CYCLES_UK 0x01430379
#define IDQ_MS_CYCLES_K  0x01420379
#define IDQ_MS_CYCLES_U  0x01410379
#define IDQ_MS_UOPS_UK   0x00430379
#define IDQ_MS_UOPS_K    0x00420379
#define IDQ_MS_UOPS_U    0x00410379
#define IDQ_MS_SWITCHES_UK 0x01470379
#define IDQ_MS_SWITCHES_K  0x01460379
#define IDQ_MS_SWITCHES_U  0x01450379
#define ICACHE_16B_IFDATA_STALL_UK 0x00430480
#define ICACHE_16B_IFDATA_STALL_K  0x00420480
#define ICACHE_16B_IFDATA_STALL_U  0x00410480
#define ICACHE_64B_IFTAG_HIT_UK    0x00430183
#define ICACHE_64B_IFTAG_HIT_K     0x00420183
#define ICACHE_64B_IFTAG_HIT_U     0x00410183
#define ICACHE_64B_IFTAG_MISS_UK   0x00430283
#define ICACHE_64B_IFTAG_MISS_K    0x00420283
#define ICACHE_64B_IFTAG_MISS_U    0x00410283
#define ICACHE_64B_IFTAG_STALL_UK  0x00430483
#define ICACHE_64B_IFTAG_STALL_K   0x00420483
#define ICACHE_64B_IFTAG_STALL_U   0x00410483
#define ITLB_MISSES_MISS_CAUSES_A_WALK_UK 0x00430185
#define ITLB_MISSES_MISS_CAUSES_A_WALK_K  0x00420185
#define ITLB_MISSES_MISS_CAUSES_A_WALK_U  0x00410185
#define ITLB_MISSES_WALK_COMPLETED_4K_UK  0x00430285
#define ITLB_MISSES_WALK_COMPLETED_4K_K    0x00420285
#define ITLB_MISSES_WALK_COMPLETED_4K_U   0x00410285
#define ITLB_MISSES_WALK_COMPLETED_2M_4M_UK 0x00430485
#define ITLB_MISSES_WALK_COMPLETED_2M_4M_K  0x00420485
#define ITLB_MISSES_WALK_COMPLETED_2M_4M_U  0x00410485
#define ITLB_MISSES_WALK_COMPLETED_1G_UK    0x00430885
#define ITLB_MISSES_WALK_COMPLETED_1G_K     0x00420885
#define ITLB_MISSES_WALK_COMPLETED_1G_U     0x00410885
#define ITLB_MISSES_WALK_COMPLETED_UK  0x00430e85
#define ITLB_MISSES_WALK_COMPLETED_K   0x00420e85
#define ITLB_MISSES_WALK_COMPLETED_U   0x00410e85
#define ITLB_MISSES_WALK_PENDING_UK    0x00431085
#define ITLB_MISSES_WALK_PENDING_K     0x00421085
#define ITLB_MISSES_WALK_PENDING_U     0x00411085
#define ITLB_MISSES_WALK_ACTIVE_UK     0x01431085
#define ITLB_MISSES_WALK_ACTIVE_K      0x01421085
#define ITLB_MISSES_WALK_ACTIVE_U      0x01411085
#define ITLB_MISSES_STLB_HIT_UK        0x00432085
#define ITLB_MISSES_STLB_HIT_K         0x00422085
#define ITLB_MISSES_STLB_HIT_U         0x00412085
#define ILD_STALL_LCP_UK     0x00430187
#define ILD_STALL_LCP_K      0x00420187
#define ILD_STALL_LCP_U      0x00410187
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK_UK 0x0183019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK_K  0x0182019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK_U  0x0181019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_3_UOP_DELIV_CORE_UK 0x0103019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_3_UOP_DELIV_CORE_K  0x0102019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_3_UOP_DELIV_CORE_U  0x0101019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_2_UOP_DELIV_CORE_UK 0x0243019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_2_UOP_DELIV_CORE_U  0x0242019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_2_UOP_DELIV_CORE_U  0x0241019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_1_UOP_DELIV_CORE_UK 0x0343019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_1_UOP_DELIV_CORE_K  0x0342019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_1_UOP_DELIV_CORE_K  0x0341019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOP_DELIV_CORE_UK    0x0443019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOP_DELIV_CORE_K     0x0442019c
#define IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOP_DELIV_CORE_U     0x0441019c
#define IDQ_UOPS_NOT_DELIVERED_CORE_UK 0x0043019c
#define IDQ_UOPS_NOT_DELIVERED_CORE_K  0x0042019c
#define IDQ_UOPS_NOT_DELIVERED_CORE_U  0x0041019c
#define UOPS_DISPATCHED_PORT_PORT_0_UK 0x004301a1
#define UOPS_DISPATCHED_PORT_PORT_0_K  0x004201a1
#define UOPS_DISPATCHED_PORT_PORT_0_U  0x004101a1
#define UOPS_DISPATCHED_PORT_PORT_1_UK 0x004302a1
#define UOPS_DISPATCHED_PORT_PORT_1_K  0x004202a1
#define UOPS_DISPATCHED_PORT_PORT_1_U  0x004102a1
#define UOPS_DISPATCHED_PORT_PORT_2_UK 0x004304a1
#define UOPS_DISPATCHED_PORT_PORT_2_K  0x004204a1
#define UOPS_DISPATCHED_PORT_PORT_2_U  0x004104a1
#define UOPS_DISPATCHED_PORT_PORT_3_UK 0x004308a1
#define UOPS_DISPATCHED_PORT_PORT_3_K  0x004208a1
#define UOPS_DISPATCHED_PORT_PORT_3_U  0x004108a1
#define UOPS_DISPATCHED_PORT_PORT_4_UK 0x004310a1
#define UOPS_DISPATCHED_PORT_PORT_4_K  0x004210a1
#define UOPS_DISPATCHED_PORT_PORT_4_U  0x004110a1
#define UOPS_DISPATCHED_PORT_PORT_5_UK 0x004320a1
#define UOPS_DISPATCHED_PORT_PORT_5_UK 0x004320a1
#define UOPS_DISPATCHED_PORT_PORT_5_K  0x004220a1
#define UOPS_DISPATCHED_PORT_PORT_5_U  0x004120a1
#define UOPS_DISPATCHED_PORT_PORT_6_UK 0x004340a1
#define UOPS_DISPATCHED_PORT_PORT_6_K  0x004240a1
#define UOPS_DISPATCHED_PORT_PORT_6_U  0x004140a1
#define UOPS_DISPATCHED_PORT_PORT_7_UK 0x004380a1
#define UOPS_DISPATCHED_PORT_PORT_7_K  0x004280a1
#define UOPS_DISPATCHED_PORT_PORT_7_U  0x004180a1
#define RESOURCE_STALLS_ANY_UK  0x004301a2
#define RESOURCE_STALLS_ANY_K   0x004201a2
#define RESOURCE_STALLS_ANY_U   0x004101a2
#define RESOURCE_STALLS_SB_UK   0x004308a2
#define RESOURCE_STALLS_SB_K    0x004208a2
#define RESOURCE_STALLS_SB_U    0x004108a2
#define CYCLES_ACTIVITY_CYCLES_L2_MISS_UK 0x014301a3
#define CYCLES_ACTIVITY_CYCLES_L2_MISS_K  0x014201a3
#define CYCLES_ACTIVITY_CYCLES_L2_MISS_U  0x014101a3
#define CYCLES_ACTIVITY_CYCLES_L3_MISS_UK 0x024302a3
#define CYCLES_ACTIVITY_CYCLES_L3_MISS_K  0x024202a3
#define CYCLES_ACTIVITY_CYCLES_L3_MISS_U  0x024102a3
#define CYCLES_ACTIVITY_STALLS_TOTAL_UK   0x044304a3
#define CYCLES_ACTIVITY_STALLS_TOTAL_K    0x044204a3
#define CYCLES_ACTIVITY_STALLS_TOTAL_U    0x044104a3
#define CYCLES_ACTIVITY_STALLS_L2_MISS_UK 0x054305a3
#define CYCLES_ACTIVITY_STALLS_L2_MISS_K  0x054205a3
#define CYCLES_ACTIVITY_STALLS_L2_MISS_U  0x054105a3
#define CYCLES_ACTIVITY_STALLS_L3_MISS_UK 0x064306a3
#define CYCLES_ACTIVITY_STALLS_L3_MISS_K  0x064206a3
#define CYCLES_ACTIVITY_STALLS_L3_MISS_U  0x064106a3
#define CYCLE_ACTIVITY_CYCLES_L1D_MISS_UK 0x084308a3
#define CYCLE_ACTIVITY_CYCLES_L1D_MISS_K  0x084208a3
#define CYCLE_ACTIVITY_CYCLES_L1D_MISS_U  0x084108a3
#define CYCLE_ACTIVITY_STALLS_L1D_MISS_UK 0x0c430ca3
#define CYCLE_ACTIVITY_STALLS_L1D_MISS_K  0x0c420ca3
#define CYCLE_ACTIVITY_STALLS_L1D_MISS_U  0x0c410ca3
#define CYCLE_ACTIVITY_CYCLES_MEM_ANY_UK  0x104310a3
#define CYCLE_ACTIVITY_CYCLES_MEM_ANY_K   0x104210a3
#define CYCLE_ACTIVITY_CYCLES_MEM_ANY_U   0x104110a3
#define CYCLE_ACTIVITY_STALLS_MEM_ANY_UK  0x144314a3
#define CYCLE_ACTIVITY_STALLS_MEM_ANY_K   0x144214a3
#define CYCLE_ACTIVITY_STALLS_MEM_ANY_U   0x144114a3
#define EXE_ACTIVITY_EXE_BOUND_0_PORTS_UK 0x004301a6
#define EXE_ACTIVITY_EXE_BOUND_0_PORTS_K  0x004201a6
#define EXE_ACTIVITY_EXE_BOUND_0_PORTS_U  0x004101a6
#define EXE_ACTIVITY_1_PORTS_UTIL_UK      0x004302a6
#define EXE_ACTIVITY_1_PORTS_UTIL_K       0x004202a6
#define EXE_ACTIVITY_1_PORTS_UTIL_U       0x004102a6
#define EXE_ACTIVITY_2_PORTS_UTIL_UK      0x004304a6
#define EXE_ACTIVITY_2_PORTS_UTIL_K       0x004204a6
#define EXE_ACTIVITY_2_PORTS_UTIL_U       0x004104a6
#define EXE_ACTIVITY_3_PORTS_UTIL_UK      0x004308a6
#define EXE_ACTIVITY_3_PORTS_UTIL_K       0x004208a6
#define EXE_ACTIVITY_3_PORTS_UTIL_U       0x004108a6
#define EXE_ACTIVITY_4_PORTS_UTIL_UK      0x004310a6
#define EXE_ACTIVITY_4_PORTS_UTIL_K       0x004210a6
#define EXE_ACTIVITY_4_PORTS_UTIL_U       0x004110a6
#define EXE_ACTIVITY_BOUND_ON_STORES_UK   0x004340a6
#define EXE_ACTIVITY_BOUND_ON_STORES_K    0x004240a6
#define EXE_ACTIVITY_BOUND_ON_STORES_U    0x004140a6
#define LSD_UOPS_UK    0x004301a8
#define LSD_UOPS_K     0x004201a8
#define LSD_UOPS_U     0x004101a8
#define LSD_CYCLES_4_UOPS_UK 0x044301a8
#define LSD_CYCLES_4_UOPS_K  0x044201a8
#define LSD_CYCLES_4_UOPS_U  0x044101a8
#define LSD_CYCLES_ACTIVE_UK 0x014301a8
#define LSD_CYCLES_ACTIVE_K  0x014201a8
#define LSD_CYCLES_ACTIVE_U  0x014101a8
#define DSB2MITE_SWITCHES_PENALTY_CYCLES_UK 0x004302ab
#define DSB2MITE_SWITCHES_PENALTY_CYCLES_K  0x004202ab
#define DSB2MITE_SWITCHES_PENALTY_CYCLES_U  0x004102ab
#define ITLB_ITLB_FLUSH_UK  0x004301ae
#define ITLB_ITLB_FLUSH_K   0x004201ae
#define ITLB_ITLB_FLUSH_U   0x004101ae
#define OFFCORE_REQUESTS_DEMAND_DATA_RD_UK 0x004301b0
#define OFFCORE_REQUESTS_DEMAND_DATA_RD_K  0x004201b0
#define OFFCORE_REQUESTS_DEMAND_DATA_RD_U  0x004101b0
#define OFFCORE_REQUESTS_DEMAND_CODE_RD_UK 0x004302b0
#define OFFCORE_REQUESTS_DEMAND_CODE_RD_K  0x004202b0
#define OFFCORE_REQUESTS_DEMAND_CODE_RD_U  0x004102b0
#define OFFCORE_REQUESTS_DEMAND_RFO_UK     0x004304b0
#define OFFCORE_REQUESTS_DEMAND_RFO_K      0x004204b0
#define OFFCORE_REQUESTS_DEMAND_RFO_U      0x004104b0
#define OFFCORE_REQUESTS_ALL_DATA_RD_UK    0x004308b0
#define OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD_UK 0x004310b0
#define OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD_K  0x004210b0
#define OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD_U  0x004110b0
#define OFFCORE_REQUESTS_ALL_REQUESTS_UK  0x004380b0
#define OFFCORE_REQUESTS_ALL_REQUESTS_K   0x004280b0
#define OFFCORE_REQUESTS_ALL_REQUESTS_U   0x004180b0
#define UOPS_EXECUTED_CYCLES_GE_4_UOPS_EXEC_UK 0x044301b1
#define UOPS_EXECUTED_CYCLES_GE_4_UOPS_EXEC_K  0x044201b1
#define UOPS_EXECUTED_CYCLES_GE_4_UOPS_EXEC_U  0x044101b1
#define UOPS_EXECUTED_CYCLES_GE_3_UOPS_EXEC_UK 0x034301b1
#define UOPS_EXECUTED_CYCLES_GE_3_UOPS_EXEC_K  0x034201b1
#define UOPS_EXECUTED_CYCLES_GE_3_UOPS_EXEC_U  0x034101b1
#define UOPS_EXECUTED_CYCLES_GE_2_UOPS_EXEC_UK 0x024301b1
#define UOPS_EXECUTED_CYCLES_GE_2_UOPS_EXEC_K  0x024201b1
#define UOPS_EXECUTED_CYCLES_GE_2_UOPS_EXEC_U  0x024101b1
#define UOPS_EXECUTED_CYCLES_GE_1_UOP_EXEC_UK  0x014301b1
#define UOPS_EXECUTED_CYCLES_GE_1_UOP_EXEC_K   0x014201b1
#define UOPS_EXECUTED_CYCLES_GE_1_UOP_EXEC_U   0x014101b1
#define UOPS_EXECUTED_STALL_CYCLES_UK  0x01c301b1
#define UOPS_EXECUTED_STALL_CYCLES_K   0x01c201b1
#define UOPS_EXECUTED_STALL_CYCLES_U   0x01c101b1
#define UOPS_EXECUTED_THREAD_UK 0x004301b1
#define UOPS_EXECUTED_THREAD_K  0x004201b1
#define UOPS_EXECUTED_THREAD_U  0x004101b1
#define UOPS_EXECUTED_CORE_UK   0x004302b1
#define UOPS_EXECUTED_CORE_K    0x004202b1
#define UOPS_EXECUTED_CORE_U    0x004102b1
#define UOPS_EXECUTED_CORE_CYCLES_NONE_UK 0x01c302b1
#define UOPS_EXECUTED_CORE_CYCLES_NONE_K  0x01c202b1
#define UOPS_EXECUTED_CORE_CYCLES_NONE_U  0x01c102b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_4_UK 0x044302b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_4_K  0x044202b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_4_U  0x044102b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_3_UK 0x034302b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_3_K  0x034202b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_3_U  0x034102b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_2_UK 0x024302b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_2_K  0x024202b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_2_U  0x024102b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_1_UK 0x014302b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_1_K  0x014202b1
#define UOPS_EXECUTED_CORE_CYCLES_GE_2_U  0x014102b1
#define UOPS_EXECUTED_X87_UK 0x004310b1
#define UOPS_EXECUTED_X87_K  0x004210b1
#define UOPS_EXECUTED_X87_U  0x004110b1
#define OFFCORE_REQUESTS_BUFFER_SQ_FULL_UK 0x004301b2
#define OFFCORE_REQUESTS_BUFFER_SQ_FULL_K  0x004201b2
#define OFFCORE_REQUESTS_BUFFER_SQ_FULL_U  0x004101b2
#define OFFCORE_RESPONSE_UK 0x004301b7
#define OFFCORE_RESPONSE_K  0x004201b7
#define OFFCORE_RESPONSE_U  0x004101b7
#define TLB_FLUSH_DTLB_THREAD_UK 0x004301bd
#define TLB_FLUSH_DTLB_THREAD_K  0x004201bd
#define TLB_FLUSH_DTLB_THREAD_U  0x004101bd
#define TLB_FLUSH_STLB_ANY_UK    0x004320bd
#define TLB_FLUSH_STLB_ANY_K     0x004220bd
#define TLB_FLUSH_STLB_ANY_U     0x004120bd
#define INST_RETIRED_ANY_P_UK    0x004300c0
#define INST_RETIRED_ANY_P_K     0x004200c0
#define INST_RETIRED_ANY_P_U     0x004100c0
#define INST_RETIRED_PREC_DIST_UK 0x004301c0
#define INST_RETIRED_PREC_DIST_K  0x004201c0
#define INST_RETIRED_PREC_DIST_U  0x004101c0
#define OTHER_ASSISTS_ANY_UK 0x00433fc1
#define OTHER_ASSITS_ANY_K   0x00423fc1
#define OTHER_ASSITS_ANY_U   0x00413fc1
#define UOPS_RETIRED_TOTAL_CYCLES_UK 0x104302c2
#define UOPS_RETIRED_TOTAL_CYCLES_K  0x104202c2
#define UOPS_RETIRED_TOTAL_CYCLES_U  0x104102c2
#define UOPS_RETIRED_STALL_CYCLES_UK 0x01c302c2
#define UOPS_RETIRED_STALL_CYCLES_K  0x01c202c2
#define UOPS_RETIRED_STALL_CYCLES_U  0x01c102c2
#define UOPS_RETIRED_RETIRE_SLOTS_UK 0x004302c2
#define UOPS_RETIRED_RETIRE_SLOTS_K  0x004202c2
#define UOPS_RETIRED_RETIRE_SLOTS_U  0x004102c2
#define MACHINE_CLEAR_COUNTS_UK  0x014701c3
#define MACHINE_CLEAR_COUNT_K    0x014601c3
#define MACHINE_CLEAR_COUNT_U    0x014501c3
#define MACHINE_CLEARS_COUNT_MEMORY_ORDERING_UK 0x004302c3
#define MACHINE_CLEARS_COUNT_MEMORY_ORDERING_K  0x004202c3
#define MACHINE_CLEARS_COUNT_MEMORY_ORDERING_U  0x004102c3
#define MACHINE_CLEARS_SMC_UK 0x004304c3
#define MACHINE_CLEARS_SMC_K  0x004204c3
#define MACHINE_CLEARS_SMC_U  0x004104c3
#define BR_INST_RETIRED_ALL_BRANCHES_UK 0x004300c4
#define BR_INST_RETIRED_ALL_BRANCHES_K  0x004200c4
#define BR_INST_RETIRED_ALL_BRANCHES_U  0x004100c4
#define BR_INST_RETIRED_CONDITIONAL_UK  0x004301c4
#define BR_INST_RETIRED_CONDITIONAL_K   0x004201c4
#define BR_INST_RETIRED_CONDITIONAL_U   0x004101c4
#define BR_INST_RETIRED_NEAR_CALL_UK    0x004302c4
#define BR_INST_RETIRED_NEAR_CALL_K     0x004202c4
#define BR_INST_RETIRED_NEAR_CALL_U     0x004102c4
#define BR_INST_RETIRED_NEAR_RETURN_UK  0x004308c4
#define BR_INST_RETIRED_NEAR_RETURN_K   0x004208c4
#define BR_INST_RETIRED_NEAR_RETURN_U   0x004108c4
#define BR_INST_RETIRED_NOT_TAKEN_UK    0x004310c4
#define BR_INST_RETIRED_NOT_TAKEN_K     0x004210c4
#define BR_INST_RETIRED_NOT_TAKEN_U     0x004110c4
#define BR_INST_RETIRED_COND_NTAKEN_UK  0x004310c4
#define BR_INST_RETIRED_COND_NTAKEN_K   0x004210c4
#define BR_INST_RETIRED_COND_NTAKEN_U   0x004110c4
#define BR_INST_RETIRED_NEAR_TAKEN_UK   0x004320c4
#define BR_INST_RETIRED_NEAR_TAKEN_K    0x004220c4
#define BR_INST_RETIRED_NEAR_TAKEN_U    0x004120c4
#define BR_INST_RETIRED_FAR_BRANCH_UK   0x004340c4
#define BR_INST_RETIRED_FAR_BRANCH_K    0x004240c4
#define BR_INST_RETIRED_FAR_BRANCH_U    0x004140c4
#define BR_MISP_RETIRED_ALL_BRANCHES_UK 0x004300c5
#define BR_MISP_RETIRED_ALL_BRANCHES_K  0x004200c5
#define BR_MISP_RETIRED_ALL_BRANCHES_U  0x004100c5
#define BR_MISP_RETIRED_CONDITIONAL_UK  0x004301c5
#define BR_MISP_RETIRED_CONDITIONAL_K   0x004201c5
#define BR_MISP_RETIRED_CONDITIONAL_U   0x004101c5
#define BR_MISP_RETIRED_NEAR_CALL_UK    0x004302c5
#define BR_MISP_RETIRED_NEAR_CALL_K     0x004202c5
#define BR_MISP_RETIRED_NEAR_CALL_U     0x004102c5
#define BR_MISP_RETIRED_NEAR_TAKEN_UK   0x004320c5
#define BR_MISP_RETIRED_NEAR_TAKEN_K    0x004220c5
#define BR_MISP_RETIRED_NEAR_TAKEN_U    0x004120c5
#define FRONTEND_RETIRED_LATENCY_GE_4_UK 0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_4_K  0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_4_U  0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_2_UK 0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_2_K  0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_2_U  0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_2_UK  0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_2_K   0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_2_U   0x004101c6
#define FRONTEND_RETIRED_STLB_MISS_UK     0x004301c6
#define FRONTEND_RETIRED_STLB_MISS_K      0x004201c6
#define FRONTEND_RETIRED_STLB_MISS_U      0x004101c6
#define FRONTEND_RETIRED_ITLB_MISS_UK     0x004301c6
#define FRONTEND_RETIRED_ITLB_MISS_K      0x004201c6
#define FRONTEND_RETIRED_ITLB_MISS_U      0x004101c6
#define FRONTEND_RETIRED_L2_MISS_UK       0x004301c6
#define FRONTEND_RETIRED_L2_MISS_K        0x004201c6
#define FRONTEND_RETIRED_L2_MISS_U        0x004101c6
#define FRONTEND_RETIRED_L1I_MISS_UK      0x004301c6
#define FRONTEND_RETIRED_L1I_MISS_K       0x004201c6
#define FRONTEND_RETIRED_L1I_MISS_U       0x004101c6
#define FRONTEND_RETIRED_DSB_MISS_UK      0x004301c6
#define FRONTEND_RETIRED_DSB_MISS_K       0x004201c6
#define FRONTEND_RETIRED_DSB_MISS_U       0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_3_UK 0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_3_K  0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_3_U  0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1_UK 0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1_K  0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1_U  0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_512_UK 0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_512_K  0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_512_U  0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_256_UK 0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_256_K  0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_256_U  0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_64_UK  0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_64_K   0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_64_U   0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_32_UK  0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_32_K   0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_32_U   0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_16_UK  0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_16_K   0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_16_U   0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_8_UK   0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_8_K    0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_8_U    0x004101c6
#define FRONTEND_RETIRED_LATENCY_GE_1_UK   0x004301c6
#define FRONTEND_RETIRED_LATENCY_GE_1_K    0x004201c6
#define FRONTEND_RETIRED_LATENCY_GE_1_U    0x004101c6
#define FP_ARITH_INST_RETIRED_SCALAR_DOUBLE_UK 0x004301c7
#define FP_ARITH_INST_RETIRED_SCALAR_DOUBLE_K  0x004201c7
#define FP_ARITH_INST_RETIRED_SCALAR_DOUBLE_U  0x004101c7
#define FP_ARITH_INST_RETIRED_SCALAR_SINGLE_UK 0x004302c7
#define FP_ARITH_INST_RETIRED_SCALAR_SINGLE_K  0x004202c7
#define FP_ARITH_INST_RETIRED_SCALAR_SINGLE_U  0x004102c7
#define FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE_UK 0x004304c7
#define FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE_K  0x004204c7
#define FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE_U  0x004104c7
#define FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE_UK 0x004308c7
#define FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE_K  0x004208c7
#define FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE_UK 0x004310c7
#define FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE_K  0x004210c7
#define FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE_U  0x004110c7
#define FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE_UK 0x004320c7
#define FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE_K  0x004220c7
#define FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE_U  0x004120c7
#define FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE_UK 0x004340c7
#define FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE_K  0x004240c7
#define FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE_U  0x004140c7
#define FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE_UK 0x004380c7
#define FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE_K  0x004280c7
#define FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE_U  0x004180c7
#define HLE_RETIRED_START_UK 0x004301c8
#define HLE_RETIRED_START_K 0x004201c8
#define HLE_RETIRED_START_U 0x004101c8
#define HLE_RETIRED_ABORTED_UK 0x004304c8
#define HLE_RETIRED_ABORTED_K  0x004204c8
#define HLE_RETIRED_ABORTED_U  0x004104c8
#define HLE_RETIRED_ABORTED_MEM_UK 0x004308c8
#define HLE_RETIRED_ABORTED_MEM_K  0x004208c8
#define HLE_RETIRED_ABORTED_MEM_U  0x004108c8
#define HLE_RETIRED_ABORTED_TIMER_UK 0x004310c8
#define HLE_RETIRED_ABORTED_TIMER_K  0x004210c8
#define HLE_RETIRED_ABORTED_TIMER_U  0x004110c8
#define HLE_RETIRED_ABORTED_UNFRIENDLY_UK 0x004320c8
#define HLE_RETIRED_ABORTED_UNFRIENDLY_K  0x004220c8
#define HLE_RETIRED_ABORTED_UNFRIENDLY_U  0x004120c8
#define HLE_RETIRED_ABORTED_MEMTYPE_UK  0x004340c8
#define HLE_RETIRED_ABORTED_MEMTYPE_K   0x004240c8
#define HLE_RETIRED_ABORTED_MEMTYPE_U   0x004140c8
#define HLE_RETIRED_ABORTED_EVENTS_UK  0x004380c8
#define HLE_RETIRED_ABORTED_EVENTS_K   0x004280c8
#define HLE_RETIRED_ABORTED_EVENTS_U   0x004180c8
#define FP_ASSISTS_ANY_UK 0x01431eca
#define FP_ASSISTS_ANY_K  0x01421eca
#define FP_ASSISTS_ANY_U  0x01411eca
#define HW_INTERRUPTS_RECEIVED_UK 0x004301cb
#define HW_INTERRUPTS_RECEIVED_K  0x004201cb
#define HW_INTERRUPTS_RECEIVED_U  0x004101cb
#define ROB_MISC_EVENTS_LBR_INSERTS_UK 0x004320cc
#define ROB_MISC_EVENTS_LBR_INSERTS_K  0x004220cc
#define ROB_MISC_EVENTS_LBR_INSERTS_U  0x004120cc
#define ROB_MISC_EVENTS_PAUSE_INST_UK  0x004340cc
#define ROB_MISC_EVENTS_PAUSE_INST_K   0x004240cc
#define ROB_MISC_EVENTS_PAUSE_INST_U   0x004140cc
// To be used with MSR 0x3F6
// MSR value 0x200
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_512_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_512_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_512_U  0x004101cd
// MSR value 0x100
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_256_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_256_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_256_U  0x004101cd
// MSR value 0x80
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_128_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_128_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_128_U  0x004101cd
// MSR value 0x40
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_64_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_64_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_64_U  0x004101cd
// MSR value 0x20
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_32_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_32_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_32_U  0x004101cd
// MSR value 0x10
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_16_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_16_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_16_U  0x004101cd
// MSR value 0x8
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_8_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_8_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_8_U  0x004101cd
// MSR value 0x4
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_4_UK 0x004301cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_4_K  0x004201cd
#define MEM_TRANS_RETIRED_LOAD_LATENCY_GT_4_U  0x004101cd
#define MEM_INST_RETIRED_STLB_MISS_LOADS_UK    0x004311d0
#define MEM_INST_RETIRED_STLB_MISS_LOADS_K     0x004211d0
#define MEM_INST_RETIRED_STLB_MISS_LOADS_U     0x004111d0
#define MEM_INST_RETIRED_STLB_MISS_STORES_UK   0x004312d0
#define MEM_INST_RETIRED_STLB_MISS_STORES_K    0x004212d0
#define MEM_INST_RETIRED_STLB_MISS_STORES_U    0x004112d0
#define MEM_INST_RETIRED_LOCK_LOADS_UK         0x004321d0
#define MEM_INST_RETIRED_LOCK_LOADS_K          0x004221d0
#define MEM_INST_RETIRED_LOCK_LOADS_U          0x004121d0
#define MEM_INST_RETIRED_SPLIT_LOADS_UK        0x004341d0
#define MEM_INST_RETIRED_SPLIT_LOADS_K         0x004241d0
#define MEM_INST_RETIRED_SPLIT_LOADS_U         0x004141d0
#define MEM_INST_RETIRED_SPLIT_STORES_UK       0x004342d0
#define MEM_INST_RETIRED_SPLIT_STORES_K        0x004242d0
#define MEM_INST_RETIRED_SPLIT_STORES_U        0x004142d0
#define MEM_INST_RETIRED_ALL_LOADS_UK          0x004381d0
#define MEM_INST_RETIRED_ALL_LOADS_K           0x004281d0
#define MEM_INST_RETIRED_ALL_LOADS_U           0x004181d0
#define MEM_INST_RETIRED_ALL_STORES_UK         0x004382d0
#define MEM_INST_RETIRED_ALL_STORES_K          0x004282d0
#define MEM_INST_RETIRED_ALL_STORES_U          0x004182d0
#define MEM_LOAD_RETIRED_L1_HIT_UK             0x004301d1
#define MEM_LOAD_RETIRED_L1_HIT_K              0x004201d1
#define MEM_LOAD_RETIRED_L1_HIT_U              0x004101d1
#define MEM_LOAD_RETIRED_L2_HIT_UK             0x004302d1
#define MEM_LOAD_RETIRED_L2_HIT_K              0x004202d1
#define MEM_LOAD_RETIRED_L2_HIT_U              0x004102d1
#define MEM_LOAD_RETIRED_L3_HIT_UK             0x004304d1
#define MEM_LOAD_RETIRED_L3_HIT_K              0x004204d1
#define MEM_LOAD_RETIRED_L3_HIT_U              0x004104d1
#define MEM_LOAD_RETIRED_L1_MISS_UK            0x004308d1
#define MEM_LOAD_RETIRED_L1_MISS_K             0x004208d1
#define MEM_LOAD_RETIRED_L1_MISS_U             0x004108d1
#define MEM_LOAD_RETIRED_L2_MISS_UK            0x004310d1
#define MEM_LOAD_RETIRED_L2_MISS_K             0x004210d1
#define MEM_LOAD_RETIRED_L2_MISS_U             0x004110d1
#define MEM_LOAD_RETIRED_L3_MISS_UK            0x004320d1
#define MEM_LOAD_RETIRED_L3_MISS_K             0x004220d1
#define MEM_LOAD_RETIRED_L3_MISS_U             0x004120d1
#define MEM_LOAD_RETIRED_FB_HIT_UK             0x004340d1
#define MEM_LOAD_RETIRED_FB_HIT_K              0x004240d1
#define MEM_LOAD_RETIRED_FB_HIT_U              0x004140d1
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS_UK   0x004301d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS_K    0x004201d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS_U    0x004101d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_HIT_UK    0x004302d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_HIT_K     0x004202d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_HIT_U     0x004102d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_HITM_UK   0x004304d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_HITM_K    0x004204d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_HITM_U    0x004104d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE_UK   0x004308d2
#define MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE_K    0x004208d2
#define MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE_U    0x004108d2
#define MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM_UK 0x004301d3
#define MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM_K  0x004201d3
#define MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM_U  0x004101d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM_UK 0x004302d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM_K  0x004202d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM_U  0x004102d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM_UK 0x004304d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM_K  0x004204d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM_U  0x004104d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD_UK  0x004308d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD_K   0x004208d3
#define MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD_U   0x004108d3
#define MEM_LOAD_MISC_RETIRED_UC_UK             0x004304d4
#define MEM_LOAD_MISC_RETIRED_UC_K              0x004204d4
#define MEM_LOAD_MISC_RETIRED_UC_U              0x004104d4
#define BACLEARS_ANY_UK   0x004301e6
#define BACLEARS_ANY_K    0x004201e6
#define BACLEARS_ANY_U    0x004101e6
#define CORE_SNOOP_RESPONSE_RSP_IHITI_UK        0x004301ef
#define CORE_SNOOP_RESPONSE_RSP_IHITI_K         0x004201ef
#define CORE_SNOOP_RESPONSE_RSP_IHITI_U         0x004101ef
#define CORE_SNOOP_RESPONSE_RSP_IHITFSE_UK      0x004302ef
#define CORE_SNOOP_RESPONSE_RSP_IHITFSE_K       0x004202ef
#define CORE_SNOOP_RESPONSE_RSP_IHITFSE_U       0x004102ef
#define CORE_SNOOP_RESPONSE_RSP_SHITFSE_UK      0x004304ef
#define CORE_SNOOP_RESPONSE_RSP_SHITFSE_K       0x004204ef
#define CORE_SNOOP_RESPONSE_RSP_SHITFSE_U       0x004104ef
#define CORE_SNOOP_RESPONSE_RSP_SFWDM_UK        0x004308ef
#define CORE_SNOOP_RESPONSE_RSP_SFWDM_K         0x004208ef
#define CORE_SNOOP_RESPONSE_RSP_SFWDM_U         0x004108ef
#define CORE_SNOOP_RESPONSE_RSP_IFWDM_UK        0x004310ef
#define CORE_SNOOP_RESPONSE_RSP_IFWDM_K         0x004210ef
#define CORE_SNOOP_RESPONSE_RSP_IFWDM_U         0x004110ef
#define CORE_SNOOP_RESPONSE_RSP_IFWDFE_UK       0x004320ef
#define CORE_SNOOP_RESPONSE_RSP_IFWDFE_K        0x004220ef
#define CORE_SNOOP_RESPONSE_RSP_IFWDFE_U        0x004120ef
#define CORE_SNOOP_RESPONSE.RSP_SFWDFE_UK       0x004340ef
#define CORE_SNOOP_RESPONSE_RSP_SFWDFE_K        0x004240ef
#define CORE_SNOOP_RESPONSE_RSP_SFWDFE_U        0x004140ef
#define L2_TRANS_L2_WB_UK  0x004340f0
#define L2_TRANS_L2_WB_K   0x004240f0
#define L2_TRANS_L2_WB_U   0x004140f0
#define L2_LINES_IN_ALL_UK 0x00431ff1
#define L2_LINES_IN_ALL_K  0x00421ff1
#define L2_LINES_IN_ALL_U  0x00411ff1
#define L2_LINES_OUT_SILENT_UK 0x004301f2
#define L2_LINES_OUT_SILENT_K  0x004201f2
#define L2_LINES_OUT_SILENT_U  0x004101f2
#define L2_LINES_OUT_NON_SILENT_UK 0x004302f2
#define L2_LINES_OUT_NON_SILENT_K  0x004202f2
#define L2_LINES_OUT_NON_SILENT_U  0x004102f2
#define L2_LINES_OUT_USELESS_HWPF_UK 0x004304f2
#define L2_LINES_OUT_USELESS_HWPF_K  0x004204f2
#define L2_LINES_OUT_USELESS_HWPF_U  0x004104f2
#define SQ_MISC_SPLIT_LOCK_UK 0x004310f2
#define SQ_MISC_SPLIT_LOCK_K  0x004210f2
#define SQ_MISC_SPLIT_LOCK_U  0x004110f2
#define IDI_MISC_WB_UPGRADE_UK 0x004302fe
#define IDI_MISC_WB_UPGRADE_K  0x004202fe
#define IDI_MISC_WB_UPGRADE_U  0x004102fe
#define IDI_MISC_WB_DOWNGRADE_UK 0x004304fe
#define IDI_MISC_WB_DOWNGRADE_K  0x004204fe
#define IDI_MISC_WB_DOWNGRADE_U  0x004104fe
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_ANY_RESPONSE_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_ANY_RESPONSE_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_ANY_RESPONSE_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_ANY_RESPONSE_MSR_VAL 0x0000010001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_MSR_VAL 0x01003C0001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_UK  0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_K   0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_U   0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_MSR_VAL 0x04003C0001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HITM_OTHER_CORE_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HITM_OTHER_CORE_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HITM_OTHER_CORE_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_HITM_OTHER_CORE_MSR_VAL 0x10003C0001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_ANY_SNOOP_MSR_VAL 0x3F803C0001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_ANY_SNOOP_MSR_VAL 0x3FBC000001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HIT_FORWARD_UK 0x004301B7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HIT_FORWARD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HIT_FORWARD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HIT_FORWARD_MSR_VAL 0x083FC00001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HITM_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HITM_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HITM_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_HITM_MSR_VAL 0x103FC00001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063FC00001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063B800001
#define OFFCORE_RESPONSE_DEMAND_RFO_ANY_RESPONSE_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_ANY_RESPONSE_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_ANY_RESPONSE_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_ANY_RESPONSE_MSR_VAL 0x0000010002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_NO_SNOOP_NEEDED_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_NO_SNOOP_NEEDED_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_NO_SNOOP_NEEDED_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_NO_SNOOP_NEEDED_MSR_VAL 0x01003C0002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HIT_OTHER_CORE_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HIT_OTHER_CORE_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HIT_OTHER_CORE_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HIT_OTHER_CORE_NO_FWD_MSR_VAL 0x04003C0002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HITM_OTHER_CORE_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HITM_OTHER_CORE_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HITM_OTHER_CORE_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_HITM_OTHER_CORE_MSR_VAL 0x10003C0002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_ANY_SNOOP_MSR_VAL 0x3F803C0002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_ANY_SNOOP_MSR_VAL 0x3FBC000002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HIT_FORWARD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HIT_FORWARD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HIT_FORWARD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HIT_FORWARD_MSR_VAL 0x083FC00002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HITM_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HITM_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HITM_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_HITM_MSR_VAL 0x103FC00002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063FC00002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063B800002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x0604000002
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_ANY_RESPONSE_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_ANY_RESPONSE_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_ANY_RESPONSE_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_ANY_RESPONSE_MSR_VAL 0x0000010004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_MSR_VAL 0x04003C0004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HITM_OTHER_CORE_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HITM_OTHER_CORE_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HITM_OTHER_CORE_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_HITM_OTHER_CORE_MSR_VAL 0x10003C0004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_ANY_SNOOP_MSR_VAL 0x3F803C0004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HIT_FORWARD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HIT_FORWARD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HIT_FORWARD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HIT_FORWARD_MSR_VAL 0x083FC00004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HITM_UK  0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HITM_K   0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HITM_U   0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_HITM_MSR_VAL 0x103FC00004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063FC00004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063B800004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_K 0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x0604000004
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_ANY_RESPONSE_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_ANY_RESPONSE_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_ANY_RESPONSE_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_ANY_RESPONSE_MSR_VAL 0x0000010010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_NO_SNOOP_NEEDED_MSR_VAL 0x01003C0010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_HIT_OTHER_CORE_NO_FWD_MSR_VAL 0x04003C0010
// MSR Index 0x1a6,0x1a7
// MSR Value 0x3F803C0010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_ANY_SNOOP_MSR_VAL 0x3F803C0010
// MSR Index 0x1a6,0x1a7
// MSR Value 0x3F803C0010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_ANY_SNOOP_MSR_VAL 0x3F803C0010
// MSR Index 0x1a6,0x1a7
// MSR Value 0x083FC00010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS.REMOTE_HIT_FORWARD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS.REMOTE_HIT_FORWARD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS.REMOTE_HIT_FORWARD_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS.REMOTE_HIT_FORWARD_MSR_VAL 0x083FC00010
// MSR Index 0x1a6,0x1a7
// MSR Value 0x103FC00010
#define  OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define  OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define  OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define  OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x103FC00010
// MSR Index 0x1a6,0x1a7
// MSR Value 0x063B800010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063B800010
// MSR Index 0x1a6,0x1a7
// MSR Value 0x0604000010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x0604000010 
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0122
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0491
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0491
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0120
#define OFFCORE_RESPONSE_ALL_PF_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_UK  0x004301b7
#define OFFCORE_RESPONSE_ALL_PF_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_K   0x004201b7
#define OFFCORE_RESPONSE_ALL_PF_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_U   0x004101b7
#define OFFCORE_RESPONSE_ALL_PF_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0120
// MSR Index 0x1a6,0x1a7
// MSR Value  0x08007C0490
#define OFFCORE_RESPONSE_ALL_PF_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_PF_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_PF_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_PF_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0490
// MSR Index 0x1a6,0x1a7
// MSR Value  0x08007C0400
#define OFFCORE_RESPONSE_PF_L1D_AND_SW_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L1D_AND_SW_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L1D_AND_SW_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L1D_AND_SW_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL  0x08007C0400
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0100
#define OFFCORE_RESPONSE_PF_L3_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_UK  0x004301b7
#define OFFCORE_RESPONSE_PF_L3_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_K   0x004201b7
#define OFFCORE_RESPONSE_PF_L3_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_U   0x004101b7
#define OFFCORE_RESPONSE_PF_L3_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0100
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0080
#define OFFCORE_RESPONSE_PF_L3_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L3_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L3_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L3_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0080
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0020
#define OFFCORE_RESPONSE_PF_L2_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0020
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0010
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_PF_L2_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0010
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0004
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_CODE_RD_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0004
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0002
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_RFO_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0002
// MSR Index 0x1a6,0x1a7
// MSR Value 0x08007C0001
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_DEMAND_DATA_RD_L3_HIT_SNOOP_HIT_WITH_FWD_MSR_VAL 0x08007C0001
// MSR Index 0x1a6,0x1a7
// MSR Value 0x0604000122
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x0604000122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x063B800122
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define  OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063B800122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x063FC00122
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063FC00122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x103FC00122
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HITM_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HITM_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HITM_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HITM_MSR_VAL 0x103FC00122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x083FC00122
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HIT_FORWARD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HIT_FORWARD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HIT_FORWARD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_REMOTE_HIT_FORWARD_MSR_VAL 0x083FC00122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x3FBC000122
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_MISS_ANY_SNOOP_MSR_VAL 0x3FBC000122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x3F803C0122
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_ANY_SNOOP_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_ANY_SNOOP_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_ANY_SNOOP_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_ANY_SNOOP_MSR_VAL 0x3F803C0122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x01003C0122
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_NO_SNOOP_NEEDED_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_NO_SNOOP_NEEDED_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_NO_SNOOP_NEEDED_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_L3_HIT_NO_SNOOP_NEEDED_MSR_VAL 0x01003C0122
// MSR Index 0x1a6,0x1a7
// MSR Value 0x0000010122
#define OFFCORE_RESPONSE_ALL_RFO_ANY_RESPONSE_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_RFO_ANY_RESPONSE_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_RFO_ANY_RESPONSE_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_RFO_ANY_RESPONSE_MSR_VAL 0x0000010122
// MSR Index 0x1a6,0x1a7
// MSR Value  0x0604000491
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_LOCAL_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_MSR_VAL 0x0604000491
// MSR Index 0x1a6,0x1a7
// MSR Value  0x063B800491
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_UK 0x004301b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_K  0x004201b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_U  0x004101b7
#define OFFCORE_RESPONSE_ALL_DATA_RD_L3_MISS_REMOTE_DRAM_SNOOP_MISS_OR_NO_FWD_MSR_VAL 0x063B800491
#endif /*__SKX_PERFEVTSEL_WRITE_MASKS_H__*/
