
#ifndef __PERFARCH_MSRs_H__
#define __PERFARCH_MSRs_H__



#define IA32_PMC0 0xC1L
#define IA32_PMC1 0xC2L
#define IA32_PMC2 0xC3L
#define IA32_PMC3 0xC4L
#define IA32_PMC4 0xC5L
#define IA32_PMC5 0xC6L
#define IA32_PMC6 0xC7L
#define IA32_PMC7 0xC8L
#define IA32_PERFEVTSEL0 0x186L
#define IA32_PERFEVTSEL1 0x187L
#define IA32_PERFEVTSEL2 0x188L
#define IA32_PERFEVTSEL3 0x189L
#define IA32_PERFEVTSEL4 0x18AL
#define IA32_PERFEVTSEL5 0x18BL
#define IA32_PERFEVTSEL6 0x18CL
#define IA32_PERFEVTSEL7 0x18DL
#define IA32_PERF_STATUS 0x198L
#define IA32_THERM_STATUS 0x19CL
#define IA32_PERF_CTL 0x199L
#define IA32_MISC_ENABLE 0x1A0L
#define IA32_FIXED_CTR0 0x309L
#define IA32_FIXED_CTR1 0x30AL
#define IA32_FIXED_CTR2 0x30BL
#define IA32_FIXED_CTR_CTRL 0x38DL
#define IA32_PERF_GLOBAL_STATUS 0x38EL
#define IA32_PERF_GLOBAL_CTRL 0x38FL
#define IA32_PERF_GLOBAL_OVF_CTRL 0x390L

#define IA32_TIME_STAMP_COUNTER 0x10L
#define MSR_SMI_COUNT 0x34L
#define IA32_MPERF 0xE7L
#define IA32_APERF 0xE8L
#define IA32_CLOCK_MODULATION 0x19AL
#define IA32_ENERGY_PERF_BIAS 0x1B0L
#define IA32_PACKAGE_THERM_STATUS 0x1B1L
#define IA32_DEBUGCTL 0x1D9L
#define IA32_PLATFORM_DCA_CAP 0x1F8L
#define IA32_CPU_DCA_CAP 0x1F9L
#define IA32_DCA_0_CAP 0x1FAL
#define IA32_PERF_CAPABILITIES 0x345L
#define IA32_PEBS_ENABLE 0x3F1L
#define IA32_A_PMC0 0x4C1L
#define IA32_A_PMC1 0x4C2L
#define IA32_A_PMC2 0x4C2L
#define IA32_A_PMC3 0x4C3L
#define IA32_A_PMC4 0x4C4L
#define IA32_A_PMC5 0x4C5L
#define IA32_A_PMC6 0x4C6L
#define IA32_A_PMC7 0x4C7L
#define IA32_TSC_AUX 0xC0000203L
// MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H
#define IA32_FEATURE_CONTROL 0x3AL
#define MSR_PLATFORM_INFO 0xCEL
#define MSR_TEMPERATURE_TARGET 0x1A2L
#define MSR_TURBO_RATIO_LIMIT  0x1ADL
#define MSR UNCORE_RATIO_LIMIT 0x620L





#endif /*__PERFARCH_MSRs_H__*/
