/*
    Copyright (c) 2026, The AROS Development Team. All rights reserved.
    $Id$

    Desc: atomic operations for 64bit risc-v processors
    Lang: english
*/

#ifndef AROS_RISCV64_ATOMIC_H
#define AROS_RISCV64_ATOMIC_H

/* The riscv implementation is width-agnostic */
#include <aros/riscv/atomic.h>

#endif /* AROS_RISCV64_ATOMIC_H */
